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Sunil Kumar Vemula

from Fremont, CA
Age ~55
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Also known as:
Sunil K Vemula, Sunil Kumar Venula, Sunil K Vermula
Related to:
Sanjay Anil Varma, 45Ajay Kumar, 52Kishen KumarGina Mechler, 58Sathish KumarAnita Malhotra, 49
Connected to:
Krishna C Vemula, 38Madhuri D Vemula, 56Raghava R Vemula, 61Rama K Vemula, 38Suman S Vemula, 59Madhuri Vemulakonda, 54Anisha Vemulapalli, 37Balaji B Vemulapalli, 45Chandra Vemulapalli, 34Himadhar Vemulapalli, 50

Sunil Vemula Phones & Addresses

  • Fremont, CA
  • 728 Sequoia Dr, Sunnyvale, CA 94086
  • 965 El Camino Real, Sunnyvale, CA 94087
  • 2275 Bascom Ave, Campbell, CA 95008
  • Santa Clara, CA
  • San Jose, CA
  • Sioux Falls, SD
  • San Bruno, CA

Work

Company: Microsoft Aug 2010 Position: Senior director of hardware engineering

Education

Degree: Master of Science, Masters School / High School: Louisiana State University 1991 to 1993 Specialities: Computer Engineering

Industries

Computer Hardware

Resumes

Resumes

Sunil Vemula Photo 1

Senior Director Of Hardware Engineering

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Location:
Campbell, CA
Industry:
Computer Hardware
Work:
Microsoft
Senior Director of Hardware Engineering
Seamicro Mar 2008 - Mar 2010
Member of Technical Staff
Netx Jun 2006 - Mar 2008
Senior Staff Engineer
Sun Microsystems Jun 2001 - Jun 2006
Senior Staff Engineer
Afara Web Systems May 2001 - Sep 2002
Memeber of Technical Staff
Education:
Louisiana State University 1991 - 1993
Master of Science, Masters, Computer Engineering Indian Institute of Technology, Kharagpur 1987 - 1991
Bachelors, Bachelor of Science, Electrical Engineering

Publications

Us Patents

System And Method For Block Write To Memory

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US Patent:
7281096, Oct 9, 2007
Filed:
Feb 9, 2005
Appl. No.:
11/054850
Inventors:
Ramaswamy Sivaramakrishnan - San Jose CA, US
Sunil Vemula - Sunnyvale CA, US
Sanjay Patel - Fremont CA, US
James P. Laudon - Madison WI, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 13/14
US Classification:
711152, 711200
Abstract:
A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.

System And Method For Memory Chip Kill

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US Patent:
7360132, Apr 15, 2008
Filed:
May 19, 2005
Appl. No.:
11/134773
Inventors:
Sunil K. Vemula - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G11C 29/00
US Classification:
714723, 714718
Abstract:
A memory interface comprising a first data input for receiving a data line to be stored in memory, a bad chip register containing a bad chip value for identifying a bad memory chip of a memory device to be used with the memory interface, and a write shift logic circuit receiving the data line from the first data input. The data line contains a plurality of data bits and a plurality of check bits, the check bits being logically appended to one end of the data bits. The write shift logic, in response to the bad chip value, causes a portion of the data line to be shifted toward the one end of the bad memory chip.

Method And Apparatus For Data Synchronization To Local Clock On Memory Reads

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US Patent:
7394721, Jul 1, 2008
Filed:
Sep 20, 2005
Appl. No.:
11/232367
Inventors:
Sunil K. Vemula - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
365233, 365191, 365194, 36518905, 711118
Abstract:
A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with writing data into a storage element asynchronously according to a first clock domain. Next, the data is read from the storage element synchronously according to a second clock domain. A microprocessor and a system wherein data is read over a bi-directional bus are included.

System And Method For Efficient Power Throttling In Multiprocessor Chip

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US Patent:
7596707, Sep 29, 2009
Filed:
May 6, 2005
Appl. No.:
11/123760
Inventors:
Sunil K. Vemula - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 1/26
G06F 1/32
US Classification:
713320, 713300, 711105, 711167
Abstract:
A method for limiting power consumption in a multiprocessor chip is provided. In this method, a read or write request is received by the memory controller, which controls a memory that is external to the multiprocessor chip. The memory controller includes a bank counter that keeps track of the number of read or write requests received by the memory controller. At every clock cycle, the bank counter value is compared with a threshold value to determine whether the counter value is equal to the threshold value. If the bank counter value is determined to be equal to the threshold value, then any subsequent incoming read or write requests are blocked. The bank counter value is incremented each time a read or write request is sent to the memory.

Mix Buffers And Command Queues For Audio Blocks

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US Patent:
20130212341, Aug 15, 2013
Filed:
Feb 13, 2013
Appl. No.:
13/766128
Inventors:
MICROSOFT CORPORATION - , US
Brian Lloyd Schmidt - Bellevue WA, US
Sunil Kumar Vemula - Sunnyvale CA, US
Robert N. Heitkamp - Sammamish WA, US
Assignee:
MICROSOFT CORPORATION - Redmond WA
International Classification:
G06F 12/00
US Classification:
711154
Abstract:
The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.

Method And Apparatus For Data Capture On A Bi-Directional Bus

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US Patent:
7196948, Mar 27, 2007
Filed:
Mar 7, 2005
Appl. No.:
11/074462
Inventors:
Sunil K. Vemula - Sunnyvale CA, US
Francis X. Schumacher - Palo Alto CA, US
Ian P. Shaeffer - San Jose CA, US
Assignee:
Sun Microsystems, Inc . - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
365193, 365191, 365194, 365233
Abstract:
A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with issuing a read command. Then, a strobe signal is transitioned from a mid-rail state. In one embodiment, the strobe signal is transitioned to a logical low state. A read enable signal is then transitioned prior to a first falling edge of the strobe signal. The strobe signal represents an earliest availability for valid read data being available. The valid read data is read in response to the read enable signal transition. A microprocessor and a system wherein data is read over a bi-directional bus are included.

Processor-Based System Employing Configurable Local Frequency Throttling Management To Manage Power Demand And Consumption, And Related Methods

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US Patent:
20220253120, Aug 11, 2022
Filed:
Feb 8, 2021
Appl. No.:
17/170418
Inventors:
- Redmond WA, US
Xiaoling XU - Cuppertino CA, US
Venkatesh BALASUBRAMANIAN - San Jose CA, US
Sunil K. VEMULA - Sunnyvale CA, US
Derek E. GLADDING - Poughquag NY, US
Cesar MALDONADO - Mountain View CA, US
International Classification:
G06F 1/324
G06F 1/08
G06F 11/30
H03L 7/08
Abstract:
Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Mix Buffers And Command Queues For Audio Blocks

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US Patent:
20170200466, Jul 13, 2017
Filed:
Mar 24, 2017
Appl. No.:
15/469480
Inventors:
- Redmond WA, US
Brian Lloyd Schmidt - Bellevue WA, US
Sunil Kumar Vemula - Sunnyvale CA, US
Robert N. Heitkamp - Sammamish WA, US
International Classification:
G11B 20/10
G06F 13/28
G10L 19/24
G06F 3/06
Abstract:
The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.
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Sunil Kumar Vemula from Fremont, CA, age ~55 Get Report