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Sunhom Steve Paak

from San Francisco, CA
Age ~63
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Also known as:
Sunhom Te Paak, Sunhom S Paak, Steve Paak Sunhom, Funho Paak, Sunhon Paak, Hom Paak Sunhom, M Paak
Related to:
Yongseok S Park, 61Keehwan Park, 42Heesoo Paak, 59Brian H Paak, 34
Connected to:
Milton F Paal, 94Sandra J Paal, 78Victoria H Paal, 41Magdalena Paala, 55Stacy L Paalanen, 52John K Paalman, 84Deepa Paammi, 48Ileana Paan, 37Gary J Paananen, 84Randi S Paananen, 51

Sunhom Paak Phones & Addresses

  • San Francisco, CA
  • Los Angeles, CA
  • 19665 Charters Ave, Saratoga, CA 95070 (408) 221-4031
  • 1034 Mount Carmel Dr, San Jose, CA 95120 (408) 927-7253
  • 3779 Blackford Ave APT 28, San Jose, CA 95117 (408) 927-7253
  • 10230 Foothill Blvd, Cupertino, CA 95014 (408) 861-0868
  • Santa Clara, CA
  • West Lafayette, IN
  • W Lafayette, IN

Resumes

Resumes

Sunhom Paak Photo 1

Senior Vice President

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Location:
19665 Charters Ave, Saratoga, CA 95070
Industry:
Semiconductors
Work:
Hisilicon Huawei Technologies
Chief Technology Officer
Zen Feb 1, 2006 - Dec 1, 2015
Founder and Chairman of Northern California Korean Zen Association
Samsung May 2010 - Dec 2015
Senior Vice President of Semiconductor Technology Development
Applied Materials Dec 1, 2008 - Dec 1, 2010
Head of Advanced Energy Technology Development
Applied Materials Dec 2008 - Apr 2009
Senior Director, Solar Group
Education:
Purdue University 1992 - 1997
Doctorates, Doctor of Philosophy Seoul National University 1980 - 1985
Bachelors, Bachelor of Arts, Physics
Skills:
Manufacturing
Market Development
Semiconductors
Soc
Ic
Solar Energy
Process Equipment
Heavy Equipment
Semiconductor Process
Silicon
Characterization
Pvd
Semiconductor Fabrication
Asic
Verilog
Engineering Management
Fpga
Failure Analysis
Thin Films
Cvd
R&D
Cmos
Cross Functional Team Leadership
Design of Experiments
Vlsi
Simulations
Product Development
Semiconductor Industry
Electronics
Analog
Integrated Circuits
Research and Development
System on A Chip
Very Large Scale Integration
Application Specific Integrated Circuits
Interests:
More Than 30 Us Patents
More Than 50 Technical Papers
Languages:
English
Korean
Mandarin
Sunhom Paak Photo 2

Senior Vice President

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Location:
San Francisco, CA
Work:

Senior Vice President
Sunhom Paak Photo 3

Senior Vice President

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Location:
San Francisco, CA
Work:

Senior Vice President
Sunhom Paak Photo 4

Sunhom Paak

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Position:
Head of Silicon Solar Technology Development at Applied Materials, Founder and Chairman at Korean Zen Center
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Applied Materials since Dec 2008
Head of Silicon Solar Technology Development
Korean Zen Center since Feb 2006
Founder and Chairman
Applied Materials Dec 2008 - Apr 2009
Sr. Director, Solar Group
Xilinx Inc. Aug 1997 - Nov 2008
Director, Technology Development Group
Education:
Purdue University 1992 - 1997
Ph.D., EE Seoul National University 1980 - 1985
BA, Physics
Skills:
Semiconductor Process and Device Technologies
Solar Technology Development
Management of Product Development Group
New Market Development
Honor & Awards:
Quarterly Excellence Award 2008, Innovation Award 2008, Technology Leadership Award 2007, Innovation Award 2007, Excellence Award 2005, Korean Government Science and Technology Teacher Award 1998

Publications

Us Patents

Non-Volatile Memory Cell Integrated With A Latch

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US Patent:
7280421, Oct 9, 2007
Filed:
Jul 6, 2006
Appl. No.:
11/483007
Inventors:
Phillip A. Young - Albuquerque NM, US
Sunhom Paak - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 7/00
US Classification:
365201, 365194, 365218
Abstract:
A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated control signal. When the control signal is de-activated, the latch is de-coupled from the first voltage supply terminal and coupled to the non-volatile memory cell. If the non-volatile memory cell is programmed, the latch is coupled to a second voltage supply terminal, thereby storing a second logic value in the latch. If the non-volatile memory cell is erased, the latch is isolated from the second voltage supply terminal, and the first logic value remains stored in the latch. The latch can also be directly written through one or more access transistors, thereby facilitating testing.

Cmos-Compatible Non-Volatile Memory Cell With Lateral Inter-Poly Programming Layer

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US Patent:
7294888, Nov 13, 2007
Filed:
Sep 30, 2005
Appl. No.:
11/240030
Inventors:
Sunhom Paak - San Jose CA, US
Boon Yong Ang - Cupertino CA, US
Hsung Jai Im - Cupertino CA, US
Daniel Gitlin - Palo Alto CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 29/76
H01L 21/336
US Classification:
257369, 438258
Abstract:
An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Shrinkable And Highly Coupled Double Poly Eeprom With Inverter

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US Patent:
7301194, Nov 27, 2007
Filed:
Nov 15, 2004
Appl. No.:
10/990066
Inventors:
Sunhom Paak - San Jose CA, US
David Kuan-Yu Liu - Fremont CA, US
Anders T. Dejenfelt - Kagerod, SE
Cyrus Chang - San Jose CA, US
Qi Lin - Cupertino CA, US
Phillip A. Young - Albuquerque NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 29/788
US Classification:
257315, 257316, 257E21422, 257E21209
Abstract:
A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.

Cost Efficient Nonvolatile Sram Cell

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US Patent:
7301811, Nov 27, 2007
Filed:
Nov 15, 2004
Appl. No.:
10/990173
Inventors:
Sunhom Paak - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 11/34
G11C 16/04
US Classification:
3651851, 36518505
Abstract:
A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in a first polysilicon layer, and a tunnel window formed in a tunnel oxide area, wherein the tunnel oxide area is covered by at least a portion of the floating gate. The control gate may control charge on the floating gate, and may be formed in a second polysilicon layer, wherein the second polysilicon layer is above the first polysilicon layer.

Test Circuit And Method Of Use Thereof For The Manufacture Of Integrated Circuits

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US Patent:
7312625, Dec 25, 2007
Filed:
Jun 8, 2006
Appl. No.:
11/449197
Inventors:
Sunhom Paak - San Jose CA, US
Hsung Jai Im - Cupertino CA, US
Boon Yong Ang - Santa Clara CA, US
Jan L. de Jong - Cupertino CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/00
US Classification:
324770, 324765
Abstract:
A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.

Efuse Resistance Sensing Scheme With Improved Accuracy

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US Patent:
7501879, Mar 10, 2009
Filed:
Mar 13, 2007
Appl. No.:
11/717836
Inventors:
Kwansuhk Oh - San Jose CA, US
Raymond C. Pang - San Jose CA, US
Hsung Jai Im - Cupertino CA, US
Sunhom Paak - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 17/18
H01H 85/00
US Classification:
327525, 3652257
Abstract:
An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.

One-Time-Programmable Logic Bit With Multiple Logic Elements

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US Patent:
7567449, Jul 28, 2009
Filed:
Oct 27, 2006
Appl. No.:
11/588775
Inventors:
Sunhom Paak - San Jose CA, US
Hsung Jai Im - Cupertino CA, US
Boon Yong Ang - Santa Clara CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G11C 17/00
US Classification:
365 96, 3652257, 36518908
Abstract:
A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Integrated Circuit With Fuse Programming Damage Detection

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US Patent:
7598749, Oct 6, 2009
Filed:
Jun 8, 2006
Appl. No.:
11/449171
Inventors:
Boon Yong Ang - Santa Clara CA, US
Sunhom Paak - San Jose CA, US
Hsung Jai Im - Cupertino CA, US
Kwansuhk Oh - San Jose CA, US
Raymond C. Pang - San Jose CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G01R 31/07
H01L 29/00
US Classification:
324550, 324537, 3652257, 365201, 257529
Abstract:
An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.
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Sunhom Steve Paak from San Francisco, CA, age ~63 Get Report