Resumes
Resumes
Massachusetts Institute Of Technology
View pageWork:
Massachusetts Institute of Technology
Sungkwon Lee Phones & Addresses
-
Dublin, CA
-
San Ramon, CA
Work
Position:
Massachusetts institute of technology
Massachusetts Institute of Technology
Publications
Us Patents
Combined Positive And Negative Voltage Electrostatic Discharge (Esd) Protection Clamp With Cascoded Circuitry
View pageUS Patent:
20210344193, Nov 4, 2021
Filed:
Apr 29, 2021
Appl. No.:
17/243744
Inventors:
- San Jose CA, US
Henry Yuan - San Ramon CA, US
Mimi Qian - Campbell CA, US
Myeongseok Lee - Campbell CA, US
Sungkwon Lee - Saratoga CA, US
Yan Yi - Mountain View CA, US
Ravindra M. Kapre - San Jose CA, US
Murtuza Lilamwala - San Jose CA, US
Henry Yuan - San Ramon CA, US
Mimi Qian - Campbell CA, US
Myeongseok Lee - Campbell CA, US
Sungkwon Lee - Saratoga CA, US
Yan Yi - Mountain View CA, US
Ravindra M. Kapre - San Jose CA, US
Murtuza Lilamwala - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H02H 9/04
H01L 27/02
H01L 27/02
Abstract:
A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.