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Sujith Kumar Arramreddy

from Saratoga, CA
Age ~60
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Also known as:
Sujith K Arramreddy, Sujith Gadiraju, Tonya Rae Soto
Phone and address:
19358 Monte Vista Dr, Saratoga, CA 95070
(408) 402-5056
Related to:
Admal C Reddy, 80Muralidhar Jammula, 59Radhika Reddy, 52
Connected to:
Venkat R Arramreddy, 62Marcy L Arrance, 58David P Arrand, 72Deborah L Arrandale, 43Jody M Arrandale, 48Kathryn R Arrand, 38Paula M Arrand, 59Talitha J Arrand, 65Berkely R Arrants, 60Jason S Arrants, 52

Sujith Arramreddy Phones & Addresses

  • 19358 Monte Vista Dr, Saratoga, CA 95070 (408) 402-5056 (408) 354-1810
  • Truckee, CA
  • 7131 Heartland Way, San Jose, CA 95135 (408) 532-7353 (408) 270-7886
  • Sunnyvale, CA
  • Cupertino, CA
  • North Las Vegas, NV
  • Santa Clara, CA

Public records

Vehicle Records

Sujith Arramreddy

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Address:
19358 Monte Vis Dr, Saratoga, CA 95070
VIN:
5FNRL38747B075331
Make:
HONDA
Model:
ODYSSEY
Year:
2007

Business Records

Name / Title
Company / Classification
Phones & Addresses
Sujith Arramreddy
DALLAS SV HEALTH CARE, LLC
4901 Monterey Dr, Frisco, TX 75034
19358 Monte Vis Dr, Saratoga, CA 95070

Publications

Us Patents

Peripheral Component Interconnect Arbiter Implementation With Dynamic Priority Scheme

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US Patent:
6826644, Nov 30, 2004
Filed:
Aug 10, 2000
Appl. No.:
09/637846
Inventors:
Sujith K. Arramreddy - San Jose CA
Assignee:
ServerWorks Corporation - Santa Clara CA
International Classification:
G06F 1314
US Classification:
710244, 710240
Abstract:
A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. The target also integrates a buffer management scheme, in one embodiment an input/output cache, for buffer management. The present invention optimizes the performance and utilization of the PCI bus.

Peripheral Component Interconnect Arbiter Implementation With Dynamic Priority Scheme

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US Patent:
7234012, Jun 19, 2007
Filed:
Oct 12, 2004
Appl. No.:
10/963061
Inventors:
Sujith K. Arramreddy - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 13/14
US Classification:
710244, 710241, 710242, 710243
Abstract:
A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. The target also integrates a buffer management scheme, in one embodiment an input/output cache, for buffer management. The present invention optimizes the performance and utilization of the PCI bus.

Methods And Apparatus For Non-Intrusive Capturing Of Frame Buffer Memory Information For Remote Display

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US Patent:
8144160, Mar 27, 2012
Filed:
Feb 14, 2008
Appl. No.:
12/031112
Inventors:
Dwarka Partani - San Jose CA, US
Sujith Arramreddy - San Jose CA, US
Balakrishna Jayadev - San Jose CA, US
Assignee:
Emulex Corporation - Costa Mesa CA
International Classification:
G09G 5/36
G06F 13/00
US Classification:
345545, 345537, 345538, 345547
Abstract:
Modification to frame buffer memory information associated with a first display may be used to update information displayed on a second display. The first display may be mapped to a matrix of display areas. The modification to the frame buffer memory information may be detected be detecting write memory address. One or more display areas affected by the modification to the frame buffer memory information may be identified based on display parameters associated with the first display. Frame buffer memory information associated with the one or more affected display areas may be retrieved and compressed before being transmitted over a communication link to be displayed on the second display.

Methods, Apparatus, And Systems For Integrated Management, Graphics And I/O Control Of Server Systems

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US Patent:
8375115, Feb 12, 2013
Filed:
Feb 14, 2008
Appl. No.:
12/030963
Inventors:
Dwarka Partani - San Jose CA, US
Sujith Arramreddy - San Jose CA, US
Assignee:
Emulex Corporation - Costa Mesa CA
International Classification:
G06F 15/173
US Classification:
709223, 709224, 709225, 713310
Abstract:
In one embodiment of the invention, a server system is disclosed for data processing having a printed circuit board with one or more processors to process data; a network interface controller coupled to the one or more processors; and a monolithic integrated circuit (IC) coupled to the one or more processors and the network interface controller. The network interface controller couples the server system to a network for remote client access to the server system. The monolithic integrated circuit couples a remote computer system to the server system via the network. The remote computer system includes a remote storage device, a remote display, a remote keyboard, and a remote mouse to allow remote control and management of the server system.

Virtual Universal Asynchronous Receiver Transmitter For Server Systems

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US Patent:
20080201501, Aug 21, 2008
Filed:
Feb 14, 2008
Appl. No.:
12/031032
Inventors:
Dwarka Partani - San Jose CA, US
Sujith Arramreddy - San Jose CA, US
Melanie Fike - Austin TX, US
International Classification:
G06F 13/38
G06F 3/00
US Classification:
710 60, 710 63
Abstract:
In one embodiment, a monolithic integrated circuit includes a first UART, a second UART, and a multiplexer. The first UART has a parallel IO interface to couple to a host system to transceive parallel data and a serial IO interface. The second UART has a parallel IO interface and a serial IO interface coupled to the serial IO interface of the first UART. The first and second UARTs convert parallel data into serial data and serial data into parallel data. The multiplexer has an output coupled to the serial input of the first UART, a first input coupled to the serial output of the second UART, a second input coupled to a serial input of a serial communication port, and a select input coupled to a control signal selectively coupling serial interfaces of first and second UARTs together for remote terminal services at a remote computer system over a network.

Hardware Cursor Snooping

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US Patent:
20080201644, Aug 21, 2008
Filed:
Feb 14, 2008
Appl. No.:
12/031056
Inventors:
Dwarka Partani - San Jose CA, US
Sujith Arramreddy - San Jose CA, US
Wilfred A. Smith - San Jose CA, US
International Classification:
G06F 3/03
US Classification:
715740
Abstract:
A feedback subsystem may be used to control the positioning of a local cursor of a display in response to receiving remote cursor movement information from a remote computer system. The feedback subsystem may send the remote cursor movement information to an operating system (OS) which may send local coordinate information to a graphics controller. Local coordinate information from the graphics controller may be used to compare with remote coordinate information received from the remote computer system. The feedback subsystem may repeatedly send the remote cursor movement information to the OS until it is determined that the local coordinate information from the graphics controller is consistent with the remote coordinate information received from the remote computer system.

Networked Storage System With Access To Any Attached Storage Device

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US Patent:
20190018814, Jan 17, 2019
Filed:
Jul 3, 2018
Appl. No.:
16/026611
Inventors:
- San Jose CA, US
Sujith Arramreddy - Saratoga CA, US
Assignee:
Attala Systems, LLC - San Jose CA
International Classification:
G06F 13/40
G06F 13/42
G06F 9/445
Abstract:
In one embodiment, a networked system includes network interface ports to couple to a computer data network, PCIe devices, bridge devices coupled to network interface ports, a PCIe network switch coupled between bridge devices and PCIe devices, and a configuration device communicatively coupled to bridge devices and PCIe devices. Ports transmit outgoing and receive incoming network traffic. PCIe devices support a function of the computer data network. Each bridge device receives incoming network traffic portions and transmits outgoing network traffic portions through a respective network interface port. PCIe network switch routes PCIe packets between the plurality of bridge devices and the plurality of PCIe devices. Configuration device configures and initializes the PCIe devices for commands and operations that originate from the bridge devices. Configuration device and the bridge devices collaborate together to provide multiple communication paths between the network ports and the plurality of PCIe devices to provide any-to-any connectivity.

Systems With Virtual Universal Asynchronous Receiver Transmitter And Methods Therefor

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US Patent:
20160028804, Jan 28, 2016
Filed:
Jul 23, 2014
Appl. No.:
14/338570
Inventors:
Dwarka Partani - San Jose CA, US
Sujith Arramreddy - San Jose CA, US
Melanie Fike - Austin TX, US
International Classification:
H04L 29/08
G06F 13/42
Abstract:
In one embodiment, a monolithic integrated circuit includes a first UART, a second UART, and a multiplexer. The first UART has a parallel IO interface to couple to a host system to transceive parallel data and a serial IO interface. The second UART has a parallel IO interface and a serial IO interface coupled to the serial IO interface of the first UART. The first and second UARTs convert parallel data into serial data and serial data into parallel data. The multiplexer has an output coupled to the serial input of the first UART, a first input coupled to the serial output of the second UART, a second input coupled to a serial input of a serial communication port, and a select input coupled to a control signal selectively coupling serial interfaces of first and second UARTs together for remote terminal services at a remote computer system over a network.
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Sujith Kumar Arramreddy from Saratoga, CA, age ~60 Get Report