Sujit Thomas Zachariah

6519499, Feb 11, 2003

Dec 30, 1999

09/475714

Sreejit Chakravarty - Mountain View CA
Sujit T. Zachariah - Santa Clara CA
Carl D. Roth - Santa Cruz CA

Intel Corporation - Santa Clara CA

G06F 1750

700110, 700121, 716 4

A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout in a two-net analysis mode includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair. Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size. In a multi-net analysis mode, overlap rectangles are determined by net-name pair. The overlap rectangles are then used to calculate critical areas for two-net and multi-net bridges for each defect size in a set of defect sizes to be analyzed.

6598211, Jul 22, 2003

Mar 30, 2001

09/823807

Sujit T. Zachariah - Santa Clara CA
Sreejit Chakravarty - Mountain View CA

Intel Corporation - Santa Clara CA

G06F 1750

716 4, 716 5

A bridge fault extractor. For one aspect, one of a plurality of segments of a hierarchically described integrated circuit layout is flattened to produce an annotated list of rectangles. A fault list corresponding to the segment is then computed using the annotated list of rectangles. The fault list is then merged with any prior-generated fault list, and the actions of flattening, computing and merging are repeated for each of the plurality of segments to produce a fault list for the integrated circuit.

6502004, Dec 31, 2002

Nov 17, 1999

09/442119

Sreejit Chakravarty - Mountain View CA
Sujit T. Zachariah - Santa Clara CA
Carl D. Roth - Santa Cruz CA

Intel Corporation - Santa Clara CA

G06F 1750

700110, 700121, 716 4

A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair. Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size.

20210350202, Nov 11, 2021

Mar 8, 2021

17/195633

SUJIT THOMAS ZACHARIAH - dublin CA, US
GOLAK BIHARI SARANGI - bangalore, IN

G06N 3/00
G06N 20/00
G06F 21/62

A computerized method for managing an artificially-intelligent platform to generate personas automatically from digital data includes the step of obtaining an analytics data set. The method includes the step of augmenting the analytics data set with additional context information provided by augmentation data, wherein the augmentation data comprises specified a set of external data sources and data models. The method includes the step of determining, with a specified machine learning algorithm, a set of behavioral insights from the augmented analytics data set. The method includes the step of automatically grouping a set of users of a web-application or web site based on their behavior, demographics, history of transactions, and psychographics. The method includes the step of generating a persona for each of the segment associated with a user of the set of user, wherein a segment is a group based on a user behavior, a user demographic, a user transactional history, a user psychographic attribute.