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Sudhir D Kadkade

from Lake Oswego, OR
Age ~66

Sudhir Kadkade Phones & Addresses

  • 4970 Centerwood St, Lake Oswego, OR 97035 (503) 620-6427
  • Westborough, MA
  • Wilsonville, OR
  • 4970 Centerwood St, Lake Oswego, OR 97035 (503) 706-0978

Work

Position: Production Occupations

Education

Degree: Associate degree or higher

Emails

Publications

Us Patents

System Verification Using One Or More Automata

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US Patent:
7290193, Oct 30, 2007
Filed:
Sep 30, 2004
Appl. No.:
10/957259
Inventors:
Sudhir Dattaram Kadkade - Lake Oswego OR, US
International Classification:
G01R 31/28
US Classification:
714742, 714741
Abstract:
A method and apparatus for manipulating a non-deterministic automaton and a traversal of a non-deterministic automaton for dynamic verification of a system or device under test is described herein.

Dynamic Verification Traversal Strategies

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US Patent:
7549100, Jun 16, 2009
Filed:
Oct 26, 2007
Appl. No.:
11/925700
Inventors:
Sudhir Dattaram Kadkade - Lake Oswego OR, US
International Classification:
G01R 31/28
US Classification:
714742
Abstract:
A method of implementing a traversal strategy as part of a dynamic verification can include initializing a non-deterministic automaton (NDA) traversal mechanism that has (1) a strategy push-down stack (strategy PDS) that holds traversal strategy pointers and (2) an object push-down stack (object PDS) that holds object pointers, pushing a traversal strategy object pointer onto the strategy PDS, wherein the traversal strategy object pointer points to a traversal strategy object, popping a current object pointer from the object PDS, and determining whether the current object pointer points to a terminal object.

Method And System For Programming Devices Using Finite State Machine Descriptions

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US Patent:
20030066050, Apr 3, 2003
Filed:
Sep 26, 2001
Appl. No.:
09/962232
Inventors:
Douglas Wang - Lake Forest CA, US
Sudhir Kadkade - Lake Oswego OR, US
Clifton Lyons - Lake Oswego OR, US
International Classification:
G06F009/44
US Classification:
717/105000
Abstract:
A method and system for capturing a Finite State Machine (FSM) description of the desired behavior of a device, and converting that description into a program that is executable by the device. In the preferred embodiment, the device is a programmable robot toy. The user enters an FSM description of the desired behavior of the robot toy using a graphical user interface running on a personal computer. When requested, the preferred embodiment compiles the FSM description into a program executable by a virtual machine running on a micro-controller inside the robot toy. This program is sent to the toy via an infrared transmitter and infrared receiver, and stored in the toy's memory. Then, when the robot toy is used, the virtual machine executes the stored program so that the toy behaves as specified by the FSM description.

Automaton Synchronization During System Verification

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US Patent:
20050081094, Apr 14, 2005
Filed:
Sep 30, 2004
Appl. No.:
10/956988
Inventors:
Sudhir Kadkade - Lake Oswego OR, US
Clifton Lyons - Lake Oswego OR, US
International Classification:
G06F011/00
US Classification:
714012000
Abstract:
A method and apparatus for synchronizing a non-deterministic automaton being processed on a computing device during dynamic verification of a system or device under test, is described herein.

Resource Management During System Verification

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US Patent:
20050081103, Apr 14, 2005
Filed:
Sep 30, 2004
Appl. No.:
10/956983
Inventors:
Sudhir Kadkade - Lake Oswego OR, US
International Classification:
G06F011/00
US Classification:
714037000
Abstract:
A method and apparatus for resource management for non-deterministic automata for dynamic verification of a system or device under test is described herein.

Coverage Based Pairwise Test Set Generation For Verification Of Electronic Designs

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US Patent:
20130007680, Jan 3, 2013
Filed:
Jan 31, 2012
Appl. No.:
13/363355
Inventors:
SUDHIR D. KADKADE - LAKE OSWEGO OR, US
ALEXANDER MATTHEW LYONS - LAKE OSWEGO OR, US
International Classification:
G06F 17/50
US Classification:
716107
Abstract:
With various implementations of the invention, test sequences are generated using a pairwise methodology. The generated test sequences are checked using a constraint solver to determine if the test sequences satisfy a set of constraints. In some implementations, the uncovered pairs for a particular input are checked using the constraint solver to determine if any pairs violate the constraints. Any pairs found to violate the constraints can be excluded from the test set. With some implementations, the uncovered pairs are sorted such that the sum of every three consecutive elements is odd.

Input Space Reduction For Verification Test Set Generation

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US Patent:
20140013290, Jan 9, 2014
Filed:
Feb 1, 2013
Appl. No.:
13/755639
Inventors:
MENTOR GRAPHICS CORPORATION - , US
Sudhir D. Kadkade - Lake Oswego OR, US
Kunal P. Ganeshpure - Wilsonville OR, US
Assignee:
MENTOR GRAPHICS CORPORATION - Wilsonville OR
International Classification:
G06F 17/50
US Classification:
716106
Abstract:
Various implementations of the invention provide for the determination of a test set that satisfies a coverage model, where portions of the search space need not be searched in order to generate the test set. With various implementations of the invention, a search space defined by a set of inputs for an electronic design and a coverage model is identified. The search space is then fractured into subspaces. Subsequently, the subspaces are solved to determine if they include at least one input sequence that satisfies the coverage constraints defined in the coverage model. The subspaces found to include at least one input sequence that satisfies these coverage constraints, are then searched for unique input sequences in order to generate a test set. Subspaces found not to include at least one input sequence that satisfies the coverage constraints may be excluded from the overall search space.

Test Case Generation Using A Constraint Graph Solver

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US Patent:
20170220455, Aug 3, 2017
Filed:
Jan 29, 2016
Appl. No.:
15/010117
Inventors:
- Wilsonville OR, US
Sudhir Kadkade - Lake Oswego OR, US
International Classification:
G06F 11/36
Abstract:
The application discloses a computing system to analyze a program to generate a control flow graph representing paths capable of being traversed through the program during execution. The computing system can translate the control flow graph into a constraint graph representation of the program. The computing system can utilize a constraint solver on the constraint graph to identify a set of test values associated with a coverage definition. The set of test values can prompt the program, during execution, to be exercised based on the coverage definition provided to the test program generation tool The computing system can generate a test program configured to provide the set of input variable values to the program.
Sudhir D Kadkade from Lake Oswego, OR, age ~66 Get Report