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Sudhind M Dhamankar

from Richardson, TX
Age ~54
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Also known as:
Sudhind D Dhamankar, D R
Connected to:
Minal M Dhamankar, 52Robin Dhamankar, 44Shilpa S Dhamdhere, 50Amit Dhameja, 47Joseph M Dhamer, 57Meg Dhamer, 64Ajay K Dhami, 54Baljit K Dhami, 56Barinder S Dhami, 61Gurjeet K Dhami, 59

Sudhind Dhamankar Phones & Addresses

  • Richardson, TX
  • 3316 Spring Mountain Dr, Plano, TX 75025 (972) 334-0988
  • 5000 K Ave, Plano, TX 75074 (972) 633-2779
  • Dallas, TX
  • 1901 Halford Ave, Santa Clara, CA 95051 (408) 983-1096
  • Colton, TX
  • 1901 Halford Ave, Santa Clara, CA 95051 (408) 761-8859

Work

Position: Service Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Sudhind Dhamankar Photo 1

Vice President Of Sales

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Location:
4256 Crestfield Dr, Richardson, TX 75082
Industry:
Semiconductors
Work:
Sankalp Semiconductor Pvt Ltd
Vice President of Sales
Sankalp Semiconductor Pvt Ltd
Director of Business Development
Dongbu Hitek 2009 - 2010
Digital Design Lead
Texas Instruments 2003 - 2009
Senior Staff Design Engineer
Lattice Semiconductor 2000 - 2003
Senior Design Engineer
Education:
St. Paul's High School, Indore
Indian Institute of Technology, Bombay
Masters, Master of Technology Devi Ahilya Vishwavidyalaya
Bachelor of Engineering, Bachelors, Electronics
Skills:
Asic
Integrated Circuit Design
Static Timing Analysis
Cmos
Mixed Signal
Analog
Rtl Design
Semiconductors
Vlsi
Soc
Verilog
Vhdl
Microprocessors
Application Specific Integrated Circuits
Simulations
Ic
Logic Synthesis
Signal Processing
Integrated Circuits
Sudhind Dhamankar Photo 2

Digital Design Services At Sankalp Semiconductors Usa Inc.

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Location:
Dallas/Fort Worth Area
Industry:
Semiconductors
Skills:
Integrated Circuit Design
Verilog
VHDL
Static Timing Analysis
Signal Processing
ASIC
RTL design
CMOS
Analog

Publications

Us Patents

Turbo Encoder With Reduced Processing Delay

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US Patent:
7051261, May 23, 2006
Filed:
Oct 29, 2002
Appl. No.:
10/282524
Inventors:
Sudhind Dhamankar - Santa Clara CA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03M 13/00
H03M 13/03
G11C 29/00
US Classification:
714755, 714786, 714702
Abstract:
A turbo encoder includes a memory for temporarily storing an incoming data sequence and an interleaved address generator (IAG) designed to generate a sequence of addresses corresponding to the interleaved data sequence. The IAG performs calculations based on the length of the incoming data sequence and is able to generate a first interleaved address by (or before) the time the incoming data sequence has completely shifted into the memory. As a result, the encoder begins to output encoded data substantially as soon as the corresponding incoming data have been received, thus substantially reducing the processing delay. In addition, each interleaved address can be generated on the fly as needed during data output. As a result, the entire set of interleaved addresses does not need to be stored, thus reducing the memory requirements for the encoder.

System And Method For Correcting An Inaccurate Clock

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US Patent:
7158904, Jan 2, 2007
Filed:
Feb 25, 2005
Appl. No.:
11/066375
Inventors:
Sudhind Dhamankar - Plano TX, US
Srinivasan Venkatraman - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 19/00
US Classification:
702 89, 702 85
Abstract:
System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Device And Method For Receiving And Processing Rf Signals, A Method For Providing Digital Calibration Values For Such A Device And A Receiver Incorporating The Device

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US Patent:
7680472, Mar 16, 2010
Filed:
Jun 21, 2007
Appl. No.:
11/766530
Inventors:
Sudhind Dhamankar - Plano TX, US
Naveen K. Yanduru - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04B 1/18
H04B 17/00
US Classification:
4551931, 455 6711, 4552261
Abstract:
A device for receiving a RF signal over multiple channels, a receiver incorporating the device, a method of providing digital calibration values for a digitally-tunable resonant circuit of the device, and a method of processing an RF signal. In one embodiment the device includes: (1) a low-noise amplifier having a digitally-tunable resonant circuit, (2) a memory configured to store digital calibration values particular to the device and (3) a time-constant controller coupled to the low-noise amplifier and configured to retrieve from the memory at least one of the digital calibration values as a function of a channel to be received and, based on the at least one, to cause the digitally-tunable resonant circuit to provide a time-constant corresponding to the channel to be received.

System And Method For Checking Analog Circuit With Digital Checker

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US Patent:
8296714, Oct 23, 2012
Filed:
Oct 16, 2009
Appl. No.:
12/580717
Inventors:
Guha Lakshmanan - Bangalore Karnataka, IN
Sudhind Dhamankar - Richardson TX, US
Vipin Sharma - San Jose CA, US
Sandeep Tare - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 17/50
G06F 11/22
G01R 31/02
US Classification:
716136, 324537
Abstract:
Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes establishing a target in the analog circuit, creating an analog target dummy for the target, creating a digital target dummy, binding the digital target dummy to the analog target dummy, and checking a value of the digital target dummy with a digital checker.

Polynomial Expander For Generating Coefficients Of A Polynomial From Roots Of The Polynomial

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US Patent:
7032162, Apr 18, 2006
Filed:
Apr 25, 2002
Appl. No.:
10/131883
Inventors:
Sudhind Dhamankar - Santa Clara CA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03M 13/00
US Classification:
714784
Abstract:
For generating coefficients of an expanded polynomial, n-roots, each respective coefficient is generated at a respective one of (n+1) coefficient storage registers at one of a first place at a right most place to a (n+1) place at a left most place. In addition, a temporary coefficient is stored as the respective coefficient that was at the first place in a prior clock cycle. Such coefficients are initialized, and then an iorder multiplier output is generated by multiplying an iorder root with the respective coefficient at the first place, and an iorder adder output is generated by adding the temporary coefficient to the iorder multiplier output. The respective coefficients at and to the right of an (i+1) place are shifted toward the right with the respective coefficient at the first place becoming the temporary coefficient. The iorder adder output then becomes the respective coefficient at the (i+1) place. Such a process is performed an (i+1) times for the iorder root with (i+1) clock cycles and for each of the n-roots, for i=1 to n, to generate the respective coefficients of the expanded polynomial.
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Sudhind M Dhamankar from Richardson, TX, age ~54 Get Report