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Sudheer K Vemulapalli

from Allen, TX
Age ~53
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Also known as:
Sudheer Kumar Vemulapalli
Phone and address:
1115 Bridgeway Ln, Allen, TX 75013
(214) 547-8299
Related to:
Yang W Cho, 89Ramesh B Vemulapalli, 62Prasada VemulapalliGeetha M Vemulapalli, 49Prameela VemulapalliSuneeta Maganti, 47Ankitha Vemu, 29
Connected to:
Anisha Vemulapalli, 38Balaji B Vemulapalli, 46Chandra Vemulapalli, 35Himadhar Vemulapalli, 51Lakshmi M Vemulapalli, 58Narendhar Vemulapalli, 51Ravi P Vemulapalli, 62Roopa Vemulapalli, 48Sridhar Vemulapally, 50Suresh B Vemulapalli, 42

Sudheer Vemulapalli Phones & Addresses

  • 1115 Bridgeway Ln, Allen, TX 75013 (214) 547-8299
  • 3901 Accent Dr, Dallas, TX 75287 (972) 306-7414
  • 3950 Spring Valley Rd, Dallas, TX 75244 (972) 778-0620
  • 3653 Briargrove Ln, Dallas, TX 75287 (972) 820-6226
  • 3939 Briargrove Ln, Dallas, TX 75287 (972) 778-0620
  • Little Elm, TX
  • Plano, TX
  • Ames, IA
  • 3653 Briargrove Ln, Dallas, TX 75287

Work

Company: Texas instruments Feb 2012 Position: Business manager, americas

Education

Degree: Master of Business Administration, Masters School / High School: The University of Texas at Austin 2009 to 2011 Specialities: Management

Skills

Soc • Mixed Signal • Semiconductors • Rf • Asic • Analog Circuit Design • Wireless • Product Development • Integrated Circuit Design • Product Management • Embedded Systems • Business Development • Engineering Management • Business Strategy • Strategic Partnerships • Leadership • Strategic Planning • Iot • Zigbee • Industrial Wireless • Low Power Wireless

Industries

Semiconductors

Resumes

Resumes

Sudheer Vemulapalli Photo 1

Business Manager, Americas

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Business Manager, Americas
Texas Instruments Mar 2009 - Jan 2012
Us Soc Design Manager, Low Power Wireless
Texas Instruments Jul 2007 - Feb 2009
Design Leader, Umts Transceiver Design For 3G Cellular Business
Texas Instruments Mar 2003 - Jul 2007
Design Manager - High-Speed Rf-Digital Design
Texas Instruments Aug 2000 - Mar 2003
Senior Design Engineer
Education:
The University of Texas at Austin 2009 - 2011
Master of Business Administration, Masters, Management Iowa State University 1993 - 1995
Master of Science, Masters, Electrical Engineering Jawaharlal Nehru Technological University 1989 - 1993
Bachelors, Bachelor of Science, Engineering, Communications
Skills:
Soc
Mixed Signal
Semiconductors
Rf
Asic
Analog Circuit Design
Wireless
Product Development
Integrated Circuit Design
Product Management
Embedded Systems
Business Development
Engineering Management
Business Strategy
Strategic Partnerships
Leadership
Strategic Planning
Iot
Zigbee
Industrial Wireless
Low Power Wireless

Business Records

Name / Title
Company / Classification
Phones & Addresses
Sudheer Vemulapalli
DCUBE TECHNOLOGIES, LLC
2832 Bluffview Dr, Lewisville, TX 75067
1115 Bridgeway Ln, Allen, TX 75013

Publications

Us Patents

System And Method For A Time Alignment Analog Notch

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US Patent:
7761068, Jul 20, 2010
Filed:
Mar 23, 2007
Appl. No.:
11/728227
Inventors:
Sameh Sameer Rezeq - Dallas TX, US
Khurram Waheed - Plano TX, US
Sudheer Vemulapalli - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01Q 11/12
H04B 1/04
US Classification:
4551273, 330280
Abstract:
System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.

Digital Phase Locked Loop With Gear Shifting

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US Patent:
7777576, Aug 17, 2010
Filed:
Jun 11, 2008
Appl. No.:
12/137332
Inventors:
Khurram Waheed - Plano TX, US
John Wallberg - Richardson TX, US
Robert Bogdan Staszewski - Garland TX, US
Sudheer Vemulapalli - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03L 7/093
H03L 7/16
US Classification:
331 17, 331 1 A, 331 16, 331 23, 331 25, 375376, 455260
Abstract:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—α) and an integral loop gain control having a programmable loop gain coefficient (rho—ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.

Digital Phase Locked Loop With Integer Channel Mitigation

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US Patent:
8050375, Nov 1, 2011
Filed:
Feb 1, 2008
Appl. No.:
12/024881
Inventors:
Robert Bogdan Staszewski - Garland TX, US
Sudheer K. Vemulapalli - Allen TX, US
John L. Wallberg - Richardson TX, US
Khurram Waheed - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03D 3/24
US Classification:
375373
Abstract:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.

Transmitter Pll With Bandwidth On Demand

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US Patent:
8126401, Feb 28, 2012
Filed:
Mar 27, 2009
Appl. No.:
12/412790
Inventors:
Robert Bogdan Staszewski - Garland TX, US
Khurram Waheed - Plano TX, US
Sudheer K. Vemulapalli - Allen TX, US
Manouchehr Entezari - Highland Village TX, US
Imran Bashir - McKinney TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04B 1/00
US Classification:
455 42, 455108, 455110, 375376
Abstract:
An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.

Phase Interpolator And A Delay Circuit For The Phase Interpolator

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US Patent:
8446198, May 21, 2013
Filed:
Apr 16, 2010
Appl. No.:
12/761419
Inventors:
Anant Shankar Kamath - Bangalore, IN
Krishnaswamy Nagaraj - Plano TX, US
Sudheer Kumar Vemulapalli - Allen TX, US
Jayawardan Janardhanan - Bangalore, IN
Karthik Subburaj - Bangalore, IN
Sujoy Chakravarty - Bangalore, IN
Vikas Sinha - Bangalore, IN
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03L 7/00
US Classification:
327161
Abstract:
Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Interpolative All-Digital Phase Locked Loop

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US Patent:
8045670, Oct 25, 2011
Filed:
Jan 30, 2008
Appl. No.:
12/022931
Inventors:
Khurram Waheed - Plano TX, US
Robert Bogdan Staszewski - Garland TX, US
John L. Wallberg - Richardson TX, US
Sudheer K. Vemulapalli - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03D 3/24
US Classification:
375376
Abstract:
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.

Circuit For High-Resolution Phase Detection In A Digital Rf Processor

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US Patent:
20060103566, May 18, 2006
Filed:
Nov 15, 2005
Appl. No.:
11/274965
Inventors:
Sudheer Vemulapalli - Allen TX, US
John Wallberg - Richardson TX, US
Prasant Vallur - Wylie TX, US
Robert Staszewski - Garland TX, US
International Classification:
H03M 1/12
US Classification:
341155000
Abstract:
A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.
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Sudheer K Vemulapalli from Allen, TX, age ~53 Get Report