Search

Stuart Bradley Molin

from Carlsbad, CA
Age ~68
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Also known as:
Stuart B Molin, Stuart E Molin, Stuart B Moil, Stuart B Nolin, Cindy Molin, Cyndy Molin, T Molin, Oiln M Stuart
Phone and address:
7698 Sitio Algodon, Carlsbad, CA 92009
(760) 943-6621
Related to:
Donald J Bernhardt
Connected to:
Alexander Molin, 36Antonia D Molin, 78Emil J Molin, 73Geralyn K Molin, 69Nicole Molin, 30Rachel A Molin, 76Sean D Molin, 43Susan R Molin, 85Vanessa M Molin, 42Aaron Molina, 47

Stuart Molin Phones & Addresses

  • 7698 Sitio Algodon, Carlsbad, CA 92009 (760) 943-6621
  • San Marcos, CA
  • Encinitas, CA
  • Sioux Falls, SD
  • San Francisco, CA
  • Oceanside, CA
  • Anaheim, CA
  • San Diego, CA
  • 7698 Sitio Algodon, Carlsbad, CA 92009

Work

Company: Silanna Oct 2016 Position: Vice president advanced development, silanna semiconductor north america

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: Uc Irvine 1979 to 1979

Skills

Ic • Analog Circuit Design • Start Ups • Integrated Circuit Design • Analog • Semiconductors • Mixed Signal • Electronics • Semiconductor Industry • Soc • Rf • Asic • Cmos • Product Management • Embedded Systems • Radio Frequency • Application Specific Integrated Circuits • Integrated Circuits

Industries

Semiconductors

Resumes

Resumes

Stuart Molin Photo 1

Vice President Advanced Development, Silanna Semiconductor North America

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Location:
Carlsbad, CA
Industry:
Semiconductors
Work:
Silanna
Vice President Advanced Development, Silanna Semiconductor North America
Silanna Oct 2015 - Oct 2016
Vice President Engineering, Silanna Semiconductor North America
Io Semiconductor Jan 2008 - Nov 2012
Co-Founder and Chief Technology Officer
Integrated Analog Solutions 2002 - 2007
Chief Executive Officer
Semtech 1997 - 2001
Director of Technology
Education:
Uc Irvine 1979 - 1979
Bachelors, Bachelor of Science In Electrical Engineering Uc Irvine 1975 - 1979
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Ic
Analog Circuit Design
Start Ups
Integrated Circuit Design
Analog
Semiconductors
Mixed Signal
Electronics
Semiconductor Industry
Soc
Rf
Asic
Cmos
Product Management
Embedded Systems
Radio Frequency
Application Specific Integrated Circuits
Integrated Circuits

Business Records

Name / Title
Company / Classification
Phones & Addresses
Stuart Molin
Principal
Integrated Analog Solution
Business Services
7698 Sitio Algodon, Carlsbad, CA 92009
Stuart Molin
President
Intergrated Analog Solutions, Inc
7698 Sitio Algodon, Carlsbad, CA 92009

Publications

Us Patents

Electrically Adjustable Resistor

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US Patent:
8009011, Aug 30, 2011
Filed:
Jun 26, 2008
Appl. No.:
12/147368
Inventors:
Stuart B. Molin - Oceanside CA, US
Paul Nygaard - Carlsbad CA, US
Assignee:
Semtech Corporation - Camarillo CA
International Classification:
H01C 10/00
US Classification:
338195, 257538, 257384, 438382, 438530
Abstract:
An electrically adjustable resistor comprises a resistive polysilicon layer dielectrically isolated from one or more doped semiconducting layers. A tunable voltage is applied to the doped semiconducting layers, causing the resistance of the polysilicon layer to vary. Multiple matched electrically adjustable resistors may be fabricated on a single substrate, tuned by a single, shared doped semiconductor layer, creating matched, tunable resistor pairs that are particularly useful for differential amplifier applications. Multiple, independently adjustable resistors may also be fabricated on a common substrate.

Semiconductor-On-Insulator With Back Side Connection

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US Patent:
8232597, Jul 31, 2012
Filed:
Jul 14, 2010
Appl. No.:
12/836506
Inventors:
Michael A. Stuber - Carlsbad CA, US
Stuart B. Molin - Carlsbad CA, US
Paul A. Nygaard - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 27/12
US Classification:
257347, 257349, 257E21564, 257E21703, 257E27112, 438149
Abstract:
Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Semiconductor-On-Insulator With Back Side Connection

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US Patent:
8357975, Jan 22, 2013
Filed:
Apr 28, 2012
Appl. No.:
13/459110
Inventors:
Michael A. Stuber - Carlsbad CA, US
Stuart B. Molin - Carlsbad CA, US
Paul A. Nygaard - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 27/01
US Classification:
257347, 257348, 257349, 257E21564, 257E21703, 257E27112
Abstract:
Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Vertical Semiconductor Device With Thinned Substrate

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US Patent:
8426258, Apr 23, 2013
Filed:
Oct 11, 2011
Appl. No.:
13/270339
Inventors:
Stuart B. Molin - Carlsbad CA, US
Michael A. Stuber - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 21/332
US Classification:
438138, 438137, 257E2137
Abstract:
A vertical semiconductor device (e. g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

Vertical Semiconductor Device With Thinned Substrate

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US Patent:
8426888, Apr 23, 2013
Filed:
Oct 11, 2011
Appl. No.:
13/270335
Inventors:
Stuart B. Molin - Carlsbad CA, US
Michael A. Stuber - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 29/66
US Classification:
257139, 257329, 257E2137
Abstract:
A vertical semiconductor device (e. g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

Trap Rich Layer For Semiconductor Devices

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US Patent:
8466036, Jun 18, 2013
Filed:
Dec 7, 2011
Appl. No.:
13/313231
Inventors:
Chris Brindle - Poway CA, US
Michael A. Stuber - Carlsbad CA, US
Stuart B. Molin - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 21/30
US Classification:
438455
Abstract:
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Thermal Conduction Paths For Semiconductor Structures

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US Patent:
8466054, Jun 18, 2013
Filed:
Dec 5, 2011
Appl. No.:
13/311454
Inventors:
Michael A. Stuber - Carlsbad CA, US
Chris Brindle - Poway CA, US
Stuart B. Molin - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 21/44
US Classification:
438598, 438599, 257E21122
Abstract:
A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.

Trap Rich Layer Formation Techniques For Semiconductor Devices

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US Patent:
8536021, Sep 17, 2013
Filed:
Nov 26, 2012
Appl. No.:
13/684623
Inventors:
Michael A. Stuber - Carlsbad CA, US
Stuart B. Molin - Carlsbad CA, US
Assignee:
IO Semiconductor, Inc. - San Diego CA
International Classification:
H01L 21/30
US Classification:
438455, 438456, 438457, 438458
Abstract:
A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.
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Stuart Bradley Molin from Carlsbad, CA, age ~68 Get Report