Stuart M Burns

6461529, Oct 8, 2002

Apr 26, 1999

09/299137

Diane C. Boyd - Lagrangeville NY
Stuart M. Burns - Brookfield CT
Hussein I. Hanafi - Basking Ridge NJ
Waldemar W. Kocon - Wappingers Falls NY
William C. Wille - Red Hook NY
Richard Wise - Beacon NY

International Business Machines Corporation - Armonk NY

H01L 213215

216 67, 216 72, 252 791, 438723, 438724, 438725, 438743, 438744

A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF , C F , and C F ; the hydrogen source is selected from CHF , CH F , CH F, and H ; the oxidant is selected from CO, CO , and O ; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas.

6593617, Jul 15, 2003

Feb 19, 1998

09/026093

Diane C. Boyd - Lagrangeville NY
Stuart M. Burns - Brookfield CT
Hussein I. Hanafi - Goldens Bridge NY
Yuan Taur - Bedford NY
William C. Wille - Red Hood NY

International Business Machines Corporation - Armonk NY

H01L 2976

257327

Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.

57599203, Jun 2, 1998

Nov 15, 1996

8/749748

Stuart Mcallister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY
Waldemar Walter Kocon - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 2100

438696

Method for creating a doped polysilicon layer of accurate shape on a sidewall of a semiconductor structure. According to the present method, a doped polysilicon film covering at least part of said semiconductor structure and of said sidewall is formed. This polysilicon film then undergoes a reactive ion etching (RIE) process providing for a high etch rate of said polysilicon film to approximately define the shape of the polysilicon layer on said sidewall. Then, said polysilicon film undergoes a second reactive ion etching process. This second reactive ion etching process is a low polysilicon etch rate process such that non-uniformities of the surface of said polysilicon film are removed by sputtering.

58952730, Apr 20, 1999

Jun 27, 1997

8/883762

Stuart M. Burns - Ridgefield CT
Hussein I. Hanafi - Goldens Bridge NY
Waldemar W. Kocon - Wappingers Falls NY
Jeffrey J. Welser - Greenwich CT

International Business Machines Corporation - Armonk NY

H01L 2100

438719

Decoupled plasma etching process used to make a protruding structure having vertical or near vertical sidewalls. The decoupled plasma etching process comprises the following steps: forming a mask on top of a semiconductor substrate defining the lateral size of the protruding structures to be formed in said substrate, feeding HCl, Cl. sub. 2 and N. sub. 2 into a plasma chamber to provide an ion plasma when applying source power, causing said ions to diffuse towards the substrate by applying a bias power such that the portions of said substrate not being covered by said mask are etched away, wherein the dosage of HCl, Cl. sub. 2 and N. sub. 2 is chosen such that newly formed portions of the sidewall surfaces are passivated by by-product of Si, Cl, and N. sub. 2 and thus become protected from further being etched. The bias power is less than 70 Watts to ensure that the etching process is predominantly chemical.

60339578, Mar 7, 2000

Oct 29, 1997

8/960247

Stuart Mcallister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY
Jeffrey J. Welser - Greenwich CT
Waldemar Walter Kocon - Wappingers Fall NY

International Business Machines Corporation - Armonk NY

H01L 21336
H01L 218238

438270

A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F. sup. 2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof.

61436356, Nov 7, 2000

Aug 16, 1999

9/374519

Diane C. Boyd - Lagrangeville NY
Stuart M. Burns - Brookfield CT
Hussein I. Hanafi - Goldens Bridge NY
Yuan Taur - Bedford NY
William C. Wille - Red Hood NY

International Business Machines Corporation - Armonk NY

H01L 213205
H01L 214763

438585

Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; implanting threshold adjust dopants and/or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; and removing at least part of the dielectric stack.

62682261, Jul 31, 2001

Jun 30, 1999

9/345647

David Angell - Poughkeepsie NY
Stuart M. Burns - Brookfield CT
Waldemar W. Kocon - Wappingers Falls NY
Michael L. Passow - Pleasant Valley NY

International Business Machines Corporation - Armonk NY

H01L 2100

438 16

A process for estimating a critical dimension of a trench formed by etching a substrate. First, a regression model is constructed for estimating the critical dimension, in which principal component loadings and principal component scores are also calculated. Next, a substrate is etched and spectral data of the etching are collected. A new principal component score is then calculated using the spectral data and the principal component loadings. Finally, the critical dimension of the trench is estimated by applying the new principal component score to the regression model.

60402105, Mar 21, 2000

Jan 26, 1998

9/013509

Stuart Mcallister Burns - Ridgefield CT
Hussein Ibrahim Hanafi - Goldens Bridge NY

International Business Machines Corporation - Armonk NY

H01L 218249
H01L 29788

438238

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.