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Steven Richard Vandervoort

from Loveland, CO
Age ~68
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Also known as:
Steven R Vandervoort, Steven Richar Et Vandervoort, Steven Te Vandervoort, Steven T Vandervoort, Steve R Vandervoort, Steve T Vandervoort
Related to:
Matthew Alan Schrager, 50Monica L Vandervoort, 35S Vandervoort, 68Tracie L Vandervoort, 68Scott Tyler Vandervoort, 32
Connected to:
Alex J Vanderweide, 48Alex S Vanderwerff, 60Alicia R Vandervelden, 41Allan L Vandertie, 86Angel M Vanderveer, 66Anita D Vandervelden, 73Anne M Vanderveer, 41Anne P Vandervort, 76Ashley Vanderwerf, 33Barry J Vanderwal, 48

Steven Vandervoort Phones & Addresses

  • Loveland, CO
  • 10025 Steeplechase Cir, Beaverton, OR 97008 (503) 579-4040
  • San Jose, CA
  • Campbell, CA
  • Mountain View, CA
  • 10025 SW Steeplechase Cir, Beaverton, OR 97008

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Publications

Us Patents

Socket Cover With Heat Flow For Surface Mount Solder Reflow

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US Patent:
20140001243, Jan 2, 2014
Filed:
Jun 29, 2012
Appl. No.:
13/539246
Inventors:
Victor Alvarez - Hillsboro OR, US
Scott K. Buttars - Aloha OR, US
Steven R. Vandervoort - Beaverton OR, US
Shijiang He - Gilbert AZ, US
International Classification:
H05K 13/04
US Classification:
2282481, 137597
Abstract:
A cover for a socket that is to be soldered to a printed circuit board is described. The socket has connections to be soldered to the printed circuit board and connections to contact a die that will be carried by the socket. The socket includes a top surface to cover the die contacts of the socket and side walls surrounding the top surface and extending toward the socket to separate the top surface from the die contacts. The top surface has a plurality of inlet vents, and the side walls have a plurality of outlet vents.

Techniques To Reduce Substrate Reflow Warpage

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US Patent:
20190103289, Apr 4, 2019
Filed:
Sep 29, 2017
Appl. No.:
15/720190
Inventors:
- Santa Clara CA, US
Steven Vandervoort - Beaverton OR, US
International Classification:
H01L 21/48
H01L 21/56
H01L 23/373
H01L 23/498
H01L 23/31
H01L 23/00
Abstract:
Apparatus and methods are provided to reduce warpage of an integrated circuit package while reflowing solder to couple a first substrate of a first electronic device with a second substrate or second electronic device. In an example, the method can include placing an anti-warpage fixture onto the first electronic device to provide a captured electronic device, placing the captured electronic device and the anti-warpage fixture on the second substrate, and reflowing the captured electronic device to the second substrate. In certain examples, the method can include limiting a clearance distance between the first substrate and the second substrate to a minimum distance.
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Steven Richard Vandervoort from Loveland, CO, age ~68 Get Report