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Steven F Schicht

from Austin, TX
Age ~56
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Also known as:
Steven Frederick Schicht, Steven E Schicht, Steven S Schicht, Steve F Schicht
Phone and address:
7317 Mitra Dr, Austin, TX 78739
(512) 301-8677
Related to:
Yenis E Schicht, 54
Connected to:
Andrew M Schichtel, 64Barratt L Schichtel, 42Emily M Schichtl, 40Jeffrey L Schiciano, 58Alice F Schick, 81Alissa A Schick, 43Ann F Schick, 73Anthony Schick, 56April A Schick, 58Betty C Schick, 78

Steven Schicht Phones & Addresses

  • 7317 Mitra Dr, Austin, TX 78739 (512) 301-8677 (512) 369-3129
  • 3401 Parmer Ln, Austin, TX 78727
  • Boise, ID
  • Urbana, IL
  • Carbondale, IL
  • Chandler, AZ
  • 7317 Mitra Dr, Austin, TX 78739 (512) 301-8677

Work

Position: Service Occupations

Education

Degree: Associate degree or higher

Industries

Semiconductors

Resumes

Resumes

Steven Schicht Photo 1

Design Engineer At Intel

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Location:
Austin, Texas Area
Industry:
Semiconductors

Publications

Us Patents

Method And Apparatus For Anticipatory Selection Of External Or Internal Addresses In A Synchronous Memory Device

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US Patent:
6366523, Apr 2, 2002
Filed:
Sep 5, 2000
Appl. No.:
09/655167
Inventors:
Jeffrey P. Wright - Boise ID
Steven F. Schicht - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 800
US Classification:
36523002, 365233, 36523008
Abstract:
A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.

In-Sheet Transceiver Testing

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US Patent:
6487681, Nov 26, 2002
Filed:
Nov 9, 1999
Appl. No.:
09/437718
Inventors:
Mark E. Tuttle - Boise ID
Rickie C. Lake - Eagle ID
Steven F. Schicht - Boise ID
John R. Tuttle - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 1100
US Classification:
714 25, 324605, 324613
Abstract:
A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described.

Method And Apparatus For Generating A Pulse

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US Patent:
RE38903, Nov 29, 2005
Filed:
Feb 14, 2002
Appl. No.:
10/055514
Inventors:
Jeffrey P. Wright - Boise ID, US
Steven F. Schicht - Austin TX, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F001/04
US Classification:
713500, 713503, 713600
Abstract:
A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger signal is also presented as an input to the passgate. When enabled, the passgate propagates the trigger signal to an output. A predetermined time after the trigger signal appears at the passgate input, a passgate control signal is turned off, thereby preventing the trigger signal from further passing through the passgate. The reset circuit is then turned on, which pulls the signal at the output of the passgate to a reference voltage, ending the pulse. Once the pulse is generated, it can be rectified and further combined with other signals to produce signals used in other parts of the circuit.

Method And Apparatus For Rfid Communication

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US Patent:
RE43918, Jan 8, 2013
Filed:
Sep 28, 2007
Appl. No.:
11/864718
Inventors:
Mark E. Tuttle - Boise ID, US
Rickie C. Lake - Meridian ID, US
Steven F. Schicht - Austin TX, US
John R. Tuttle - Longmont CO, US
Assignee:
Round Rock Research, LLC - Mt. Kisco NY
International Classification:
G06F 11/00
US Classification:
714 25, 324605, 324613
Abstract:
p-00010000.

Method And Apparatus For Rfid Communication

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US Patent:
RE43935, Jan 15, 2013
Filed:
Sep 28, 2007
Appl. No.:
11/864708
Inventors:
Mark E. Tuttle - Boise ID, US
Rickie C. Lake - Meridian ID, US
Steven F. Schicht - Austin TX, US
John R. Tuttle - Longmont CO, US
Assignee:
Round Rock Research, LLC - Mt. Kisco NY
International Classification:
G06F 11/00
US Classification:
714 25, 324605, 324613
Abstract:
p-00010000.

Method And Apparatus For Rfid Communication

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US Patent:
RE43940, Jan 22, 2013
Filed:
Sep 28, 2007
Appl. No.:
11/864715
Inventors:
Mark E. Tuttle - Boise ID, US
Rickie C. Lake - Meridian ID, US
Steven F. Schicht - Austin TX, US
John R. Tuttle - Longmont CO, US
Assignee:
Round Rock Research, LLC - Mt. Kisco NY
International Classification:
G06F 11/00
US Classification:
714 25, 324605, 324613
Abstract:
p-00010000.

Method And Apparatus For Communicating With Rfid Devices Coupled To A Roll Of Flexible Material

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US Patent:
RE42872, Oct 25, 2011
Filed:
Nov 24, 2004
Appl. No.:
10/997556
Inventors:
Mark E. Tuttle - Boise ID, US
Rickie C. Lake - Meridian ID, US
Steven F. Schicht - Austin TX, US
John R. Tuttle - Boulder CO, US
Assignee:
Round Rock Research, LLC - Mt. Kisco NY
International Classification:
G06F 11/00
US Classification:
714 25, 324605, 324613
Abstract:
p-00010000.

Method And Apparatus For Anticipatory Selection Of External Or Internal Addresses In A Synchronous Memory Device

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US Patent:
61153141, Sep 5, 2000
Filed:
Jun 15, 1999
Appl. No.:
9/333814
Inventors:
Jeffrey P. Wright - Boise ID
Steven F. Schicht - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 800
US Classification:
36523002
Abstract:
A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.
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Steven F Schicht from Austin, TX, age ~56 Get Report