US Patent:
20190190456, Jun 20, 2019
Inventors:
- Waltham MA, US
Valery S. Kaper - Winchester MA, US
Steven M. Lardizabal - Westford MA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H03F 1/02
H03F 3/193
H01L 29/20
H03F 1/22
H03F 3/345
H03F 1/30
Abstract:
A circuit having (A) a transistor, (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.