Steven M Douskey

6448835, Sep 10, 2002

Sep 6, 2001

09/947602

Steven Michael Douskey - Rochester MN
Bruce George Rudolph - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 104

327295, 327176

An apparatus and method for providing a gated output timing signal within a gated clock distribution tree. In accordance with the present invention, a gated clock splitter includes a timing signal input and a combinatorial logic block coupled to the timing signal input that generates a gated timing signal. A gating signal input is coupled to the combinatorial logic block for selectively enabling and disabling the output from the combinatorial logic block. A gate control circuit is coupled to the gating signal input for providing a gate signal to the combinatorial logic block, wherein the gate control circuit provides a full-cycle path for said gate signal to the gating signal input.

6711706, Mar 23, 2004

Dec 20, 2000

09/746610

Steven Michael Douskey - Rochester MN
Frank David Ferraiolo - Essex Junction VT
Michael Stephen Floyd - Leander TX

International Business Machines Corporation - Armonk NY

G01R 3128

714724, 714 30, 714733, 714734

A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0s on their drive interfaces, and setting all receive interfaces on the chips to receive 0s and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0s, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking test is then repeated for any additional interfaces that require testing.

6735543, May 11, 2004

Nov 29, 2001

09/996839

Steven Michael Douskey - Rochester MN
Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex Junction VT
Curtis Walter Preuss - Rochester MN
Robert James Reese - Austin TX
Paul William Rudrud - Rochester MN
James Donald Ryan - Rochester MN
Robert Russell Williams - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 1900

702120, 702123, 702126, 702185, 326 30, 326 31, 326 86, 714715, 714724, 714728, 324601, 324712, 324 7655, 324 7682, 716 1, 716 4

An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

6807645, Oct 19, 2004

Feb 4, 2002

10/066825

Frank William Angelotti - Rochester MN
Steven Michael Douskey - Rochester MN

International Business Machines Corporation - Armonk NY

G01R 3128

714732, 714729, 714733

A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics. First multiplexers are respectively coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A first multiple input signature register (MISR) including multiple MISR inputs is coupled to a respective one of the plurality of sequential channels under test. A blocker function is configured for blocking all MISR inputs except for a single MISR input receiving the test data output of the last sequential channel responsive to a recirculate control signal. A second MISR shadow register is coupled to the first multiple input signature register.

7114109, Sep 26, 2006

Mar 11, 2004

10/798912

James Fred Daily - Chatfield MN, US
Steven Michael Douskey - Rochester MN, US
Michael John Hamilton - Rochester MN, US

International Business Machines Corporation - Armonk NY

G01R 31/28

714724

A method and apparatus are provided for customizing and monitoring multiple interfaces, such as, multiple IEEE 1149. 1 standard joint test access group (JTAG) interfaces and implementing enhanced fault tolerance and isolation features. A first interface is connected to a pair of master sources. A second interface is connected to a plurality of target interfaces; and a third interface is provided for a plurality of predefined control signals. A pair of redundant selectors is provided for coupling a select signal to the first multiplexer for selecting one of the plurality of target interfaces. A pair of redundant ATTENTION monitor functions is provided for monitoring ATTENTION signals for each of the plurality of target interfaces.

7310278, Dec 18, 2007

May 4, 2006

11/418052

Arthur A. Bright - Croton-on-Hudson NY, US
Paul G. Crumley - Yorktown Heights NY, US
Marc B. Dombrowa - Bronx NY, US
Steven M. Douskey - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Steven F. Oakland - Colchester VT, US
Michael R. Ouellette - Westford VT, US
Scott A. Strissel - Byron MN, US

International Business Machines Corporation - Armonk NY

G11C 29/00
G11C 7/10
G11C 17/18
H03K 19/00

365200, 36518902, 36518905, 365201, 3652257, 326 10, 326 16, 714718

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

7397709, Jul 8, 2008

Oct 15, 2007

11/872088

Arthur A. Bright - Croton-on-Hudson NY, US
Paul G. Crumley - Yorktown Heights NY, US
Marc B. Dombrowa - Bronx NY, US
Steven M. Douskey - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Steven F. Oakland - Colchester VT, US
Michael R. Ouellette - Westford VT, US
Scott A. Strissel - Byron MN, US

International Business Machines Corporation - Armonk NY

G11C 7/10
G11C 29/00
G11C 17/18
H03K 19/003
G06F 11/00

36518902, 36518905, 365200, 365201, 3652257, 326 9, 326 10, 326 16, 714 6

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

7405990, Jul 29, 2008

Oct 15, 2007

11/872085

Arthur A. Bright - Croton-on-Hudson NY, US
Paul G. Crumley - Yorktown Heights NY, US
Marc B. Dombrowa - Bronx NY, US
Steven M. Douskey - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Steven F. Oakland - Colchester VT, US
Michael R. Ouellette - Westford VT, US
Scott A. Strissel - Byron MN, US

International Business Machines Corporation - Armonk NY

G11C 17/18
G11C 7/10
G11C 8/00
H03K 19/003
H03K 19/00

3652257, 36518902, 365200, 365201, 36523003, 326 9, 326 10, 326 16

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.