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Stephen S Yole

from North Kingstown, RI
Age ~66
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Also known as:
Stephen Saunders Yole, Stephen Saunders Yole Lt, Stephen Saunders Yole Living, Stephen P Gaffney, Steve Yole
Phone and address:
673 Hatchery Rd, North Kingstown, RI 02852
(401) 295-7612
Related to:
Danielle Magee
Connected to:
Mary C Yole, 65Susan M Yolen, 65Barbara A Yoli, 70Edward J Yoli, 46Gina M Yoli, 55Angela Yolich, 44James A Yolich, 49John F Yolich, 64Michaelene Yolich, 46Bruce R Yolken, 64

Stephen Yole Phones & Addresses

  • 673 Hatchery Rd, North Kingstown, RI 02852 (401) 295-7612
  • N Kingstown, RI
  • Exeter, RI
  • Jamestown, RI
  • West Warwick, RI
  • Braintree, MA
  • Dorchester, MA
  • 673 Hatchery Rd, North Kingstown, RI 02852

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Interests

job inquiries, expertise requests, busin...

Industries

Semiconductors

Resumes

Resumes

Stephen Yole Photo 1

Design Center Director At International Rectifier Director Ri Design Center At International Rectifier

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Location:
Providence, Rhode Island Area
Industry:
Semiconductors
Experience:
International Rectifier (Public Company; 1001-5000 employees; Semiconductors industry): Design Center Director,  (-) International Rectifier (Public Company; Semiconductors industry): Director RI Design Center,  (2004-Present) 

Publications

Us Patents

High Speed Totem Pole Fet Driver Circuit With Differential Cross Conduction Prevention

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US Patent:
58960589, Apr 20, 1999
Filed:
Mar 31, 1997
Appl. No.:
8/829004
Inventors:
Christopher John Sanzo - Providence RI
Jeffrey Gordon Dumas - West Warwick RI
Stephen Saunders Yole - North Kingstown RI
Assignee:
Cherry Semiconductor Corporation - East Greenwich RI
International Classification:
H03K 1760
US Classification:
327432
Abstract:
A high speed totem pole FET driver circuit with differential cross-conduction prevention. The driver circuit includes first and second switching elements coupled to a first node, and third and fourth switching elements coupled to a second node. The first node is coupled to a first current source, a pulldown circuit, and the input of the third switching element. The second node is coupled to a second current source, a pullup circuit, and the input of the second switching element. Trigger inputs are applied to the inputs of the first and fourth switching elements to switch the first and fourth switches ON and OFF, wherein the two trigger inputs are of opposite phase so that when one input is HIGH (LOW) the other input is LOW (HIGH). The second switching element may include a comparator circuit with its non-inverting input coupled to the second node, its inverting input coupled to a power source via a V. sub. BE circuit, and its output coupled to a fifth switching element, where the fifth switching element is coupled to the first node.

High Speed Logic Gate With Simulated Open Collector Output

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US Patent:
47218673, Jan 26, 1988
Filed:
Apr 16, 1986
Appl. No.:
6/852833
Inventors:
William E. Headen - West Warwick RI
Stephen S. Yole - West Warwick RI
Assignee:
Cherry Semiconductor Corporation - East Greenwich RI
International Classification:
H03K 19088
H03K 19084
H03K 1900
H03K 301
US Classification:
307456
Abstract:
A high speed logic gate is disclosed in which the voltage across the output transistor is clamped by a diode, a current switch transistor, a resistor connected between the diode and the transistor and a resistor connected to ground. A selectable high impedance is provided to enable the output of the logic gate to simulate an open collector output.
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Stephen S Yole from North Kingstown, RI, age ~66 Get Report