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Stephen A Neuendorffer

from San Jose, CA
Age ~49
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Also known as:
Stephen Andrew Neuendorffer, Stephen Te Neuendorffer, Stephen C Neuendorffer, Andrea S Neuendorffer, Stephen N Keller, Stephen Andrew R
Phone and address:
322 Los Pinos Way, San Jose, CA 95119
(408) 226-2213
Related to:
Bettina D NeuendorfferDawn E Neuendorffer, 42Arthur C Neuendorffer, 78Carl NeuendorfferPeter R Keller, 84Christina L Keller, 51Corita K Waters, 46Margaret N Newfield, 76Cynthia Keller, 53Maryjane J NeuendorfferJames F Keller, 54Ruth NeuendorfferJ A NeuendorfferCarolyn R Neuendorffer, 76Andrea S Neuendorffer, 46Mary M Keller, 86Joseph A Neuendorffer
Connected to:
Amy J Neuendorf, 42Benjamin Neuendorf, 53David J Neuendorf, 41Emily Neuendorf, 36Erich Neuendorff, 64Jayne Neuendorf, 70Joy E Neuendorff, 69Robert G Neuendorf, 62Andreas F Neuenfeldt, 62Dennis J Neuenfeldt, 82

Stephen Neuendorffer Phones & Addresses

  • 322 Los Pinos Way, San Jose, CA 95119 (408) 226-2213
  • Camp Connell, CA
  • Redmond, WA
  • Oakland, CA
  • 2104 Harwood Rd, District Heights, MD 20747 (301) 350-2164
  • El Cerrito, CA
  • Bellevue, WA
  • Alexandria, VA

Work

Company: Xilinx Jul 2016 Position: Principal engineer

Education

School / High School: University of California, Berkeley 1998 to 2004

Skills

Fpga

Industries

Semiconductors

Resumes

Resumes

Stephen Neuendorffer Photo 1

Principal Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Xilinx
Principal Engineer
Xilinx Jul 2013 - Jun 2016
Principal Engineer and Hls Product Architect
Xilinx Jan 2012 - Jun 2013
Hls Product Architect
Xilinx Oct 2004 - Dec 2011
Researcher
Uc Berkeley 1998 - 2004
Student
Education:
University of California, Berkeley 1998 - 2004
University of Maryland 1993 - 1998
Bachelors, Bachelor of Science, Electrical Engineering, Computer Science
Skills:
Fpga

Publications

Us Patents

Validating Partial Reconfiguration Of An Integrated Circuit

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US Patent:
7541833, Jun 2, 2009
Filed:
Oct 9, 2007
Appl. No.:
11/973781
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Brandon J. Blodget - Santa Clara CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 41
Abstract:
Approaches for validating a configuration bitstream used for partially reconfiguring an ingrated circuit such as a programmable logic device (PLD) are disclosed. In one approach, the integrated circuit is configured with a first configuration bitstream that includes first bit values that produce an implementation of a static part of a design on the integrated circuit. Any differences between a bit value in a second configuration bitstream and a corresponding bit value of the implementation of the static part of the design are determined. The second configuration bitstream includes second bit values that produce an implementation of a reconfigurable part of the design on the integrated circuit. A first signal state is output in response to determining that there are no differences, and a second signal state is output in response to determining that there are differences.

Profiling Circuit Arrangement

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US Patent:
7653762, Jan 26, 2010
Filed:
Oct 4, 2007
Appl. No.:
11/973037
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Peter Oruba - Dresden, DE
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G06F 3/00
US Classification:
710 18, 710305
Abstract:
Various approaches for tracing events in an electronic system are disclosed. In one approach, a circuit arrangement includes a bus, a random access memory (RAM), a plurality of programmable logic resources, and coupled configuration memory cells. A circuit arrangement is implemented in the programmable logic. The circuit arrangement receives a plurality of event indication signals from an application circuit and writes event data to the RAM in response to a change in the state of any one of the event indication signals. A bus interface circuit is coupled to the bus and to the read port of the RAM. Responsive to a read transaction on the bus for the RAM, the bus interface circuit reads data from the RAM and outputs the data on the bus in a reply bus transaction.

Relocatable Circuit Implemented In A Programmable Logic Device

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US Patent:
7765512, Jul 27, 2010
Filed:
Mar 25, 2008
Appl. No.:
12/054724
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Parimal Patel - San Antonio CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 16, 716 12, 716 13, 716 14, 716 15, 712 37, 711165, 710305, 326 41
Abstract:
A circuit is implemented using a programmable logic device (PLD) that includes an array of programmable logic and routing resources. The circuit includes a processor, a configuration port, a relocatable circuit, and an interface circuit. The processor accesses an address space using read and write transactions issued on an interface bus. The programmable logic and interconnect resources are configurable via the configuration port. The relocatable circuit is implemented in a selected region within the array by configuring the programmable logic and interconnect resources in the selected region with configuration data via the configuration port. The interface circuit translates the transactions accessing a portion of the address space assigned to the relocatable circuit into a fixed address space of the relocatable circuit. The configuration data for implementing the relocatable circuit is independent of the portion of the address space assigned to the relocatable circuit.

Interface Generation For Coupling To A High-Bandwidth Interface

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US Patent:
7834658, Nov 16, 2010
Filed:
Apr 18, 2006
Appl. No.:
11/405895
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Paul M. Hartke - Stanford CA, US
Paul R. Schumacher - Berthoud CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 712 34, 712 35, 712220
Abstract:
Method and apparatus for communication of data is described. More particularly, generation of an interface for coupling to an auxiliary processor unit for communication of data in an integrated circuit is described. Programmable logic is programmed to provide a hardware interface for communicating the data between memory and a user-defined circuit. The data is communicated at least in part via an auxiliary processor unit coupled to the hardware interface. The programming includes configuring the programmable logic to use the auxiliary processor unit to respond to coded instructions executed by a central processing unit through the provided hardware interface.

Dataflow Fifo Communication Buffer Using Highly-Multiported Memories

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US Patent:
7869452, Jan 11, 2011
Filed:
Jul 19, 2007
Appl. No.:
11/880160
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H04L 12/28
H04L 12/56
H04L 1/00
H04L 12/26
US Classification:
370414, 370416, 370418, 3702351
Abstract:
A FIFO communication system is provided using a FIFO and connection circuit to transmit data from a single source to multiple sinks. The connection circuit operates to enable simultaneous reads by the multiple sinks with a single output port FIFO. Multiple FIFOs can likewise be used to distribute data from a single source to multiple sinks without requiring a simultaneous read by both sinks. Similarly, a multiple output port FIFO can be used to supply multiple sinks without requiring simultaneous reads and without requiring additional memory use.

Multi-Rate Simulation Scheduler For Synchronous Digital Circuits In A High Level Modeling System

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US Patent:
7895026, Feb 22, 2011
Filed:
Aug 16, 2007
Appl. No.:
11/893570
Inventors:
Sean A. Kelly - Boulder CO, US
Stephen A. Neuendorffer - San Jose CA, US
Haibing Ma - Superior CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 9/455
G06F 1/00
US Classification:
703 14, 703 13, 703 15, 703 16, 703 17, 703 23, 716 2, 716 4, 716 6, 716 7, 716 18, 713500
Abstract:
A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.

Hardware Interface In An Integrated Circuit

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US Patent:
7969187, Jun 28, 2011
Filed:
Aug 6, 2010
Appl. No.:
12/851903
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Paul M. Hartke - Palo Alto CA, US
Paul R. Schumacher - Berthoud CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 41, 326 47, 712 34, 712 35, 712220
Abstract:
A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit.

Method And Apparatus For Implementing A Dataflow Circuit Model Using Application-Specific Memory Implementations

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US Patent:
8020139, Sep 13, 2011
Filed:
Dec 9, 2008
Appl. No.:
12/331212
Inventors:
Stephen A. Neuendorffer - San Jose CA, US
Ian D. Miller - Charlotte NC, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716136, 716138, 716100
Abstract:
Method, apparatus, and computer readable medium for implementing a circuit model in an integrated circuit are described. In some examples, the circuit model includes a communication channel between actors. Data portions of at least one data object passed between the actors over the communication channel are identified. An implementation is generated for the circuit model in which data portions are assigned to either local queue storage of the communication channel or centralized shared storage of the communication channel based on levels of access thereof by the actors.
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Stephen A Neuendorffer from San Jose, CA, age ~49 Get Report