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Stefan P Jackowski

from Endicott, NY
Age ~72
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Also known as:
Stefan J Jackowski, Stefan A Jackowski, Paul Jackowski, Stacy Jackowski, Jackowski Stefan
Phone and address:
115 Edwards St, Endicott, NY 13760
(607) 785-7614
Related to:
Earl A BetzAntonella Jackowski, 59Cheryl Jackowski, 55Roseann Jackowski, 80Steven Jackowski, 56
Connected to:
Barbara A Jackowski, 81Candace N Jackowski, 47Dariusz Jackowski, 55Edward P Jackowski, 54Grzegorz L Jackowski, 72Mark M Jackowski, 43Melissa S Jackowski, 45Patricia Jackowski, 60Peter L Jackowski, 74Travis J Jackowski, 29

Stefan Jackowski Phones & Addresses

  • 115 Edwards St, Endicott, NY 13760 (607) 785-7614
  • 7033 Wyers Point Rd, Ovid, NY 14521 (607) 532-9423
  • 7133 Wyers Point Rd, Ovid, NY 14521 (607) 532-9423
  • Secaucus, NJ
  • 115 W Edwards St, Endicott, NY 13760 (607) 761-5627

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Stefan Jackowski Photo 1

Stefan Jackowski

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Location:
Endicott, NY
Industry:
Computer Hardware
Work:
Ibm 1976 - 2008
Senior Engineer
Education:
Binghamton University 1973 - 1979
Master of Science, Masters, Computer Science Manhattan College 1969 - 1973
Skills:
Debugging
Storage
Embedded Systems
Cloud Computing
System Architecture
Shell Scripting
Distributed Systems
Solaris
Testing
Software Engineering
Software Design
Architectures
Hardware
Tcp/Ip
Perl
Stefan Jackowski Photo 2

Stefan Jackowski

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Publications

Us Patents

System And Method For Supporting Access To Multiple I/O Hub Nodes In A Host Bridge

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US Patent:
6920519, Jul 19, 2005
Filed:
May 10, 2000
Appl. No.:
09/569059
Inventors:
Bruce Leroy Beukema - Hayfield MN, US
Timothy Carl Bronson - Vestal NY, US
Ronald Edward Fuhs - Rochester MN, US
Glenn David Gilda - Binghamton NY, US
Anthony J Bybell - Carrboro NC, US
Stefan Peter Jackowski - Endicott NY, US
Phillip G Williams - Owego NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F013/36
G06F003/00
G06F012/00
US Classification:
710306, 710 3, 710 38, 710311, 711202
Abstract:
Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.

Opaque Memory Region For I/O Adapter Transparent Bridge

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US Patent:
6968415, Nov 22, 2005
Filed:
Mar 29, 2002
Appl. No.:
10/113299
Inventors:
Timothy C. Bronson - Vestal NY, US
Stefan P. Jackowski - Endicott NY, US
John M. Sheplock - Raleigh NC, US
Phillip G. Williams - Owego NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F013/36
US Classification:
710306, 710 29, 710 36, 710 52, 711 2, 345564
Abstract:
An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Protecting Isolated Secret Data Of Integrated Circuit Devices

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US Patent:
20100132048, May 27, 2010
Filed:
Nov 26, 2008
Appl. No.:
12/323670
Inventors:
William E. Hall - Clinton CT, US
Stefan P. Jackowski - Endicott NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 21/00
US Classification:
726 27
Abstract:
A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.

Multimode Data System For Transferring Control And Data Information In An I/O Subsystem

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US Patent:
50974106, Mar 17, 1992
Filed:
Dec 30, 1988
Appl. No.:
7/292399
Inventors:
Richard L. Hester - Brackney PA
Stefan P. Jackowski - Endicott NY
Peter N. James - Algonquin IL
James T. Moyer - Endwell NY
Robert G. Rush - Endicott NY
Gregory S. Ulsh - Endicott NY
Mark J. Wolski - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1314
US Classification:
395275
Abstract:
A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.

Error Windowing For Storage Subsystem Recovery

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US Patent:
55398758, Jul 23, 1996
Filed:
Dec 30, 1994
Appl. No.:
8/367389
Inventors:
James W. Bishop - Endicott NY
Mark L. Ciacelli - Endicott NY
Patrick W. Gallagher - Rochester MN
Stefan P. Jackowski - Endicott NY
Gregory R. Klouda - Endwell NY
Robert D. Siegl - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
G06F 1100
US Classification:
3951821
Abstract:
In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.

Failure Detection Method And Apparatus

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US Patent:
45802653, Apr 1, 1986
Filed:
Jun 30, 1983
Appl. No.:
6/509699
Inventors:
David N. Gooding - Endicott NY
Stefan P. Jackowski - Endicott NY
James T. Moyer - Endwell NY
James W. Plant - Endwell NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1110
US Classification:
371 49
Abstract:
A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.

Shared Access Control Device For Integrated System With Multiple Functional Units Accessing External Structures Over Multiple Data Buses

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US Patent:
60386304, Mar 14, 2000
Filed:
Mar 24, 1998
Appl. No.:
9/047139
Inventors:
Eric M. Foster - Owego NY
Dennis E. Franklin - Endicott NY
Stefan P. Jackowski - Endicott NY
David Wallach - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
710132
Abstract:
A multi-path access control device for an integrated system is presented which allows simultaneous access to multiple external devices coupled thereto by multiple functional units. The multiple functional units are coupled to the shared access control device across two or more high speed, shared data buses. The control device includes multiple bus ports, each coupled to a different data bus, and a non-blocking crossbar switch coupled to the bus ports for controlling forwarding, with zero cycle latency, of requests from the functional units. Multiple external device ports are coupled to the non-blocking crossbar switch for receiving requests forwarded by the crossbar switch, and each external device is coupled to a different external device port. The crossbar switch allows multiple requests at the bus ports directed to different external devices to be forwarded to different external device ports for simultaneous accessing of different external devices coupled thereto pursuant to the multiple requests.

Error Recovery In A Multiple 170 Channel Computer System

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US Patent:
53033515, Apr 12, 1994
Filed:
Mar 23, 1992
Appl. No.:
7/856832
Inventors:
Stefan P. Jackowski - Endicott NY
Ronald B. Jenkins - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1314
US Classification:
395275
Abstract:
The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control means are provided for monitoring the status of each channel and each port in order to achieve expeditious transfers through a selected port between the channel and peripheral devices. Error reporting is limited to the area directly affected by the error, and immediate disconnection helps to isolate the error and allow time for error recovery before the particular channel or port again becomes available.
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Stefan P Jackowski from Endicott, NY, age ~72 Get Report