Stanislav P Bajuk

7080344, Jul 18, 2006

Jun 25, 2003

10/604071

Stanislav Peter Bajuk - Colchester VT, US
Jack Robert Smith - South Burlington VT, US
Sebastian Theodore Ventrone - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50

716 16, 716 3, 717141, 717142, 717143, 717144, 717136

A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

20060190908, Aug 24, 2006

Mar 15, 2006

11/375891

Stanislav Bajuk - Colchester VT, US
Jack Smith - South Burlington VT, US
Sebastian Ventrone - South Burlington VT, US

G06F 17/50

716018000

A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

62497766, Jun 19, 2001

Sep 22, 1998

9/158268

Stanislav P. Bajuk - Austin TX
Cathy L. Blouin - Franklin VT
Gregory A. Blunt - Essex Junction VT
Gary D. Boldman - Jericho VT
Robert C. Juba - Manasas VA
Daniel A. McAuliffe - Burlington VT
Peter J. Miller - Essex Junction VT
Stephanie A. Miraglia - Burlington VT
Thomas C. Richardson - Huntington VT

International Business Machines Corporation - Armonk NY

G06F 1760

705400

A method of, computer system for, and computer program product for causally relating costs to products, including relating costs to a wafer having semiconductor chips comprising identifying resource costs for manufacturing the wafer including identifying equipment costs, computing load factors for each of the resource costs (the computing load factors for the equipment costs comprising determining a number of exposure fields on the wafer, computing a raw processing time for the wafer based on the number of exposure fields, and determining a percentage the raw processing time represents of a manufacturing time period on an equipment element, the equipment element having the equipment costs), producing weighted resource costs based on the resource costs and the load factors, (the producing weighted resource costs for the equipment costs comprising multiplying the equipment costs by the percentage), summing the weighted resource costs for the wafer, determining a volume of the wafer manufactured, and dividing the weighted resource costs by the volume to produce a weighted cost per wafer.

63245272, Nov 27, 2001

Sep 22, 1998

9/158478

Stanislav P. Bajuk - Austin TX
Cathy L. Blouin - Franklin VT
Gregory A. Blunt - Essex Junction VT
Gary D. Boldman - Jericho VT
Robert C. Juba - Manassas VA
Daniel A. McAuliffe - Burlington VT
Peter J. Miller - Essex Junction VT
Stephanie A. Miraglia - Burlington VT
Thomas C. Richardson - Huntington VT

International Business Machines Corporation - Armonk NY

G06F 1760

705400

A method of, computer system for, and computer program product for causally relating costs to products comprises, identifying resource costs for manufacturing the product, computing load factors for each of the resource costs, producing weighted resource costs based on the resource costs and the load factors, summing the weighted resource costs for the product, determining a volume of the product manufactured, and dividing the weighted resource costs by the volume to produce a weighted cost per product.

54846722, Jan 16, 1996

Jan 25, 1995

8/378767

Stanislav P. Bajuk - Madison WI
David S. O'Grady - Jericho VT
Edward T. Smith - Somerville MA

International Business Machines Corporation - Armonk NY

G03F 900

430 5

A method of forming rim type phase-shift lithography mask (140) involving backside overexposure of a positive resist layer (130) overlying a patterned light-blocking layer (120). By subjecting the resist layer to electromagnetic radiation (132) (e. g. , broad band UV) transmitted via the backside (115) of the mask substrate (112), portions (134) of the resist layer extending from peripheral edges of the light blocking layer inwardly a selected distance are activated. After developing activated portions of the resist layer, the "pull back" of the resist layer is transferred to the underlying light blocking layer by anisotropically etching portions of the light blocking layer not covered by the resist layer, thereby forming the desired rim structure.