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Sruthi Muralidharan Phones & Addresses

  • Wilsonville, OR
  • Hillsboro, OR
  • Clifton Park, NY
  • Troy, NY

Publications

Us Patents

Multiplexed Pulse Modulation Using Superposition

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US Patent:
20130336659, Dec 19, 2013
Filed:
Jan 10, 2012
Appl. No.:
14/002198
Inventors:
Partha S. Dutta - Clifton Park NY, US
Sruthi Muralidharan - Troy NY, US
Assignee:
RENSSELAER POLYTECHNIC INSTITUTE - Troy NY
International Classification:
H04J 14/08
US Classification:
398 98, 370345
Abstract:
The present invention relates to an optical transmitter for transmitting data. The optical transmitter includes a pulse generator for generating N data streams overlapping in time from a de-multiplexed data source. Each respective data stream has pulses with shapes unique to that respective data stream. The transmitter also includes an optical source optically transmitting an output pulse that is generated by summing the uniquely shaped pulses from each respective data stream that are overlapping in time. Each output pulse represents N bits of the data source, where N>1.

Finfet Semiconductor Structures And Methods Of Fabricating Same

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US Patent:
20170263733, Sep 14, 2017
Filed:
May 30, 2017
Appl. No.:
15/608283
Inventors:
- Grand Cayman, KY
Bingwu LIU - Clifton Park NY, US
Johannes Marinus VAN MEER - Delmar NY, US
Sruthi MURALIDHARAN - Troy NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 29/66
H01L 21/3213
H01L 21/324
H01L 21/02
H01L 29/78
H01L 21/265
H01L 21/266
H01L 21/268
H01L 21/3105
Abstract:
The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

Epitaxial Block Layer For A Fin Field Effect Transistor Device

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US Patent:
20160163862, Jun 9, 2016
Filed:
Feb 1, 2016
Appl. No.:
15/012760
Inventors:
- Grand Cayman, KY
Richard J. Carter - Saratoga Springs NY, US
Andy Wei - Queensbury NY, US
Qi Zhang - Mechanicville NY, US
Sruthi Muralidharan - Troy NY, US
Amy L. Child - Wilton NY, US
Assignee:
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
H01L 29/78
H01L 29/06
H01L 29/161
H01L 29/24
H01L 29/66
H01L 29/08
Abstract:
Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Finfet Semiconductor Structures And Methods Of Fabricating Same

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US Patent:
20150115371, Apr 30, 2015
Filed:
Oct 21, 2014
Appl. No.:
14/519215
Inventors:
- Grand Cayman, KY
Bingwu LIU - Ballston Spa NY, US
Johannes Marinus VAN MEER - Delmar NY, US
Sruthi MURALIDHARAN - Troy NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 29/78
H01L 21/3105
H01L 21/266
H01L 21/324
H01L 29/66
H01L 21/02
US Classification:
257401, 438283
Abstract:
The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

Overlay Performance For A Fin Field Effect Transistor Device

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US Patent:
20150076653, Mar 19, 2015
Filed:
Sep 17, 2013
Appl. No.:
14/028724
Inventors:
- Grand Cayman, KY
Andy Wei - Queensbury NY, US
Qi Zhang - Mechanicville NY, US
Richard J. Carter - Saratoga Springs NY, US
Hongliang Shen - Ballston Lake NY, US
Daniel Pham - Clifton Park NY, US
Sruthi Muralidharan - Troy NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 21/308
H01L 29/06
H01L 21/762
US Classification:
257506, 438424
Abstract:
Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Epitaxial Block Layer For A Fin Field Effect Transistor Device

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US Patent:
20150021695, Jan 22, 2015
Filed:
Jul 17, 2013
Appl. No.:
13/944048
Inventors:
- Grand Cayman, KY
Richard J. Carter - Saratoga Springs NY, US
Andy Wei - Queensbury NY, US
Qi Zhang - Mechanicville NY, US
Sruthi Muralidharan - Troy NY, US
Amy L. Child - Wilton NY, US
International Classification:
H01L 29/66
H01L 29/78
H01L 21/02
US Classification:
257368, 438283
Abstract:
Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.
Sruthi R Muralidharan from Wilsonville, OR, age ~39 Get Report