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Srinivasu Erukula

from Folsom, CA
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Also known as:
Rinivasu Erukula, U A
Connected to:
Ravi K Erukulla, 62Imelda F Erum, 49Darren E Erutti, 55Darlene M Ervanowitz, 66Larry D Ervans, 81Donna L Ervast, 59Mikael Ervasti, 27Andrew S Ervay, 54Christine F Ervelli, 72Larry E Erven, 80

Srinivasu Erukula Phones & Addresses

  • Folsom, CA
  • Hillsboro, OR
  • 6823 Cottingham Ln, Centreville, VA 20121
  • Manassas, VA
  • Aldie, VA
  • Sterling, VA
  • Bristow, VA
  • Tempe, AZ

Work

Company: Arizona state university Aug 2011 Address: Tempe Position: Research/lab aide

Education

Degree: Master's School / High School: Arizona State University 2010 to 2011 Specialities: Mixed Signal Circuit Design

Skills

Mixed Signal Design • Verilog • Systemverilog • Layout • Lvs • Drc • Cadence Virtuoso • Pspice • Spectre • Asic • Fpga • Xilinx • Aldec Hdl • C • Perl • Unix • Shell Scripting • Matlab • Statistics • Word • Powerpoint • Rtl Coding • Hardware Design • Memory Design • Synopsys Design Compiler • Excel • Modelsim • Outlook • Vlsi • Circuit Design • Hardware Verification • Ic • Microsoft Office • Web Development • Testing • Validation • Analog Circuit Design • Digital Design • Rtl Design • Cmos • Mixed Signal • Analog Design • Digital Electronics • Pll • Sram • Computer Architecture • Labview • Eda • Simulink • Simulation

Interests

Verification • Logic Design • Low Power Design • Circuit Design

Industries

Semiconductors

Resumes

Resumes

Srinivasu Erukula Photo 1

Senior Supplier Quality And Reliability Engineer

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Location:
6501 northeast Cherry Dr, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Arizona State University - Tempe since Aug 2011
Research/Lab Aide
Arizona State University - Tempe Aug 2010 - Aug 2011
Graduate Research Assistant
Arizona State University - polytechnic campus Jul 2010 - Aug 2010
Matlab programmer
Arizona State University - Tempe Feb 2010 - May 2010
Web Graphic Designer
Vector Institute - India Jan 2008 - Aug 2008
Digital Logic Design Intern
Education:
Arizona State University 2010 - 2011
Master's, Mixed Signal Circuit Design Jawaharlal Nehru Technological University 2004 - 2008
Jawaharlal Nehru Technological University, Electrical & Electronics Engineering
Skills:
Mixed Signal Design
Verilog
Systemverilog
Layout
Lvs
Drc
Cadence Virtuoso
Pspice
Spectre
Asic
Fpga
Xilinx
Aldec Hdl
C
Perl
Unix
Shell Scripting
Matlab
Statistics
Word
Powerpoint
Rtl Coding
Hardware Design
Memory Design
Synopsys Design Compiler
Excel
Modelsim
Outlook
Vlsi
Circuit Design
Hardware Verification
Ic
Microsoft Office
Web Development
Testing
Validation
Analog Circuit Design
Digital Design
Rtl Design
Cmos
Mixed Signal
Analog Design
Digital Electronics
Pll
Sram
Computer Architecture
Labview
Eda
Simulink
Simulation
Interests:
Verification
Logic Design
Low Power Design
Circuit Design
Control profile
Srinivasu Erukula from Folsom, CA Get Report