Srinath L Audityan

6516420, Feb 4, 2003

Oct 25, 1999

09/426265

Srinath Audityan - Austin TX
Chris Randall Stone - Austin TX
Ritesh Radheshyam Agrawal - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1342

713400, 375370, 327145

A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.

6847990, Jan 25, 2005

May 17, 2002

10/150671

Srinath Audityan - Austin TX, US
Marie J. Sullivan - Leander TX, US
Jose M. Nunez - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 1328

709212

A data transfer unit is able to read data from a source at the source coherency granule size and write data at the destination coherency granule size even though the two granule sizes may be different. A data transfer unit has registers for storing the granule size information in preparation of performing a transfer of a data block between a source and a destination. The data block is transferred in sub-blocks. Except for the first and last sub-blocks, the sub-blocks, for a read, are sized to the source coherency granule size, which is the transfer size that has been optimized for the source. For the write, the sub-blocks are sized to the destination coherency granule size, which is the transfer size that has been optimized for the destination. Thus, both the read and the write are optimized even though the transfers themselves are among devices with different coherency granules.

6898682, May 24, 2005

Aug 12, 2002

10/217174

James A. Welker - Austin TX, US
Srinath Audityan - Austin TX, US
Jose M. Nunez - Austin TX, US
Robert C. Podnar - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F012/00

711163, 365233

In response to a clock cycle and a pending READ command for data with a variably recurring access latency, a clock cycle count is adjusted. If a latency value has not been locked and if the READ command is a first READ command, the clock cycle count is stored as a locked latency value upon receiving a synchronized data available event (DQS for instance). Each subsequent READ command has an associated clock cycle count to enable pipelining wherein the clock cycle count for each READ starts incrementing when the individual READ command is issued. For subsequent READ commands, if the cycle count compares favorably with the locked latency value, data can be sampled safely from the interface at the identical latency for every READ request issued. The locked latency value can be read and/or written by software/hardware such that the read latency is consistent across multiple devices for reproducibility during debug.

20030233609, Dec 18, 2003

Jun 18, 2002

10/173757

Gus Ikonomopoulos - Austin TX, US
Srinath Audityan - Austin TX, US

H03M013/00

714/758000

Portions of error checking circuitry (-) are replicated so that the accumulated information () which is error checked in parallel may include any number of packets boundaries at any location. The location of packet boundaries, which may be information provided from system interconnect for a receiver, is used to control routing (e.g. MUXes ) and the selection of one or more final checksum(s) (-). In one embodiment, CRC checker circuitry () uses multiple XOR trees (-) along with a system of controlled routing multiplexers () and final_checksum select logic () to perform error checking on accumulated information which may include any number of packets boundaries at any location.

63178060, Nov 13, 2001

May 20, 1999

9/315612

Srinath Audityan - Austin TX
Thomas Albert Petersen - Austin TX
Robert Charles Podnar - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1200

711101

A queuing apparatus associated with a processor includes at least one static queue (11), an index generator (34), at least one index queue (37), and a static queue accessing arrangement. Each static queue (11) has a number of static queue locations (12), each for storing a static queue entry and an availability indicator (14) for indicating an availability status of the respective static queue location. The index generator (34) uses information from the static queue (11) to provide a unique index value for each static queue entry, the index value for a particular static queue entry identifying the static queue location (12) containing the particular static queue entry. Each index queue (37, 42) has a number of index queue locations (40), each for storing one of the index values provided by the index generator (34). The static queue accessing arrangement retrieves a selected index value from a particular index queue location (40), and uses the selected index value to retrieve the static queue entry with which the selected index value is associated. Multiple index queues (37, 42) facilitate prioritization of static queue entries, and reprioritization by transferring index queue values from one index queue to another.

62567136, Jul 3, 2001

Apr 29, 1999

9/303365

Srinath Audityan - Austin TX
James Nolan Hardage - Kyle TX
Thomas Albert Petersen - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1200

711141

The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.