Srikanth Balaji Samavedam

6423632, Jul 23, 2002

Jul 21, 2000

09/621804

Srikanth B. Samavedam - Austin TX
Philip J. Tobin - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2144

438652, 438655, 438656, 438657, 438682, 438683, 438592, 257751, 257755, 257754

A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion lies between the first and third conductive portions. The first conductive portion includes a first element, and the third conductive portion includes a metal and silicon without a significant amount of the first element. In another embodiment, the conductor is a gate electrode or a capacitor electrode. The conductor includes a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion. The second conductive portion lies between the first and third conductive portions and has a different composition compared to the first, third, and fourth conductive portion. The third conductive portion lies between the second and fourth conductive portions and has a different composition compared to the first and fourth conductive portions.

6475841, Nov 5, 2002

Jun 2, 2000

09/584963

Srikanth B. Samavedam - Austin TX
Nigel Cave - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 21311

438197, 438735, 438738

A transistor structure includes a retrograde gate structure ( ) that is narrower at the end that interfaces with the gate dielectric ( ) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure ( ) is formed by depositing a layer of gate material ( ) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure ( ) such that increased etching of the gate material ( ) occurs near the interface with the gate dielectric layer ( ).

6514808, Feb 4, 2003

Nov 30, 2001

09/997358

Srikanth B. Samavedam - Austin TX
Christopher C. Hobbs - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 21336

438197, 438287, 438299, 438301, 438424, 438439

A transistor device ( ) utilizes a high K dielectric ( ) between a gate electrode ( ) and a substrate ( ). The high K dielectric ( ) is etched under the gate electrode ( ) so that there is an area between the gate electrode ( ) and the substrate ( ) that is void of high K dielectric ( ). The source/drains extensions ( and ) are minimized to extend substantially in alignment with the edge of gate dielectric ( ) to reduce overlap with the gate dielectric ( ). This results in reduced capacitance between the gate and the source/drain extensions. The void areas ( and ) between the gate and the substrate ( ) may remain void or may be filled with a low K dielectric, or at least a dielectric that is not high K.

6790719, Sep 14, 2004

Apr 9, 2003

10/410043

Olubunmi O. Adetutu - Austin TX
Eric D. Luckowski - Round Rock TX
Srikanth B. Samavedam - Austin TX

Freescale Semiconductor, Inc. - Austin TX

H01L 21337

438195, 438216, 438233, 438199

A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.

6894353, May 17, 2005

Jul 31, 2002

10/209523

Srikanth B. Samavedam - Austin TX, US
Philip J. Tobin - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L029/76

257365, 257412, 438275, 438283

A first gate () and a second gate () are preferably PMOS and NMOS transistors, respectively, formed in an n-type well () and a p-type well (). In a preferred embodiment first gate () includes a first metal layer () of titanium nitride on a gate dielectric (), a second metal layer () of tantalum silicon nitride and a silicon containing layer () of polysilicon. Second gate () includes second metal layer () of a tantalum silicon nitride layer on the gate dielectric () and a silicon containing layer () of polysilicon. First spacers () are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers () need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.

6897095, May 24, 2005

May 12, 2004

10/843850

Olubunmi O. Adetutu - Austin TX, US
Srikanth B. Samavedam - Austin TX, US
Bruce E. White - Round Rock TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L021/8238

438119, 438217, 438227, 438231, 438302, 438305, 257493, 257497, 257506, 257511, 257521

A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer.

6972224, Dec 6, 2005

Mar 27, 2003

10/400896

David C. Gilmer - Austin TX, US
Srikanth B. Samavedam - Austin TX, US
Philip J. Tobin - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L021/8238

438199, 438216, 438279, 438585

A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (), such as HfO, is deposited on a semiconductor substrate. A sacrificial layer (), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area () of the substrate is exposed and gate dielectric over a second (nMOS, for example) area () of the substrate continues to be protected by the sacrificial layer. A first gate conductor material () is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

7445976, Nov 4, 2008

May 26, 2006

11/420525

James K. Schaeffer - Austin TX, US
Rama I. Hegde - Austin TX, US
Srikanth B. Samavedam - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438197, 438199, 438151

A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.