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Srikanth Jagannathan

from Austin, TX
Age ~43
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Also known as:
Srikanth Jagannadhan
Related to:
Ann CravenRosemary E Hansen, 60
Connected to:
Chakravarty Jagannath, 40Jayashree Jagannath, 47Maheshkumar Jagannathan, 40Manjunath T Jagannatharao, 53Poorna Jagannathan, 52Prashanth Jagannath, 43Radhika Jagannathan, 41Rangaswamy Jagannathan, 67Shruthi Jagannath, 35Srinath Jagannathan, 60

Srikanth Jagannathan Phones & Addresses

  • Austin, TX
  • Nashville, TN
  • Hillsboro, OR

Work

Company: Tid degradation

Education

School / High School: Vanderbilt University Jun 2009 Specialities: M.S in Electrical Engineering

Resumes

Resumes

Srikanth Jagannathan Photo 1

Principal Engineer

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Nxp Semiconductors
Principal Engineer
Freescale Semiconductor Dec 1, 2013 - Jan 2018
Analog Design and Verification Engineer at Nxp Semiconductors
Nxp Semiconductors 2015 - 2016
Ams Design and Verification
Vanderbilt University Jan 2011 - Nov 2013
Characterization of Radiation Effects on High-Speed Quadrature Lc-Vco
Vanderbilt University Jun 2012 - Jan 2013
Evaluation of Tid Sensitivity on Lna Architecture
Education:
University of North Texas at Dallas 2018 - 2020
Master of Business Administration, Masters, Management Vanderbilt University 2007 - 2013
Doctorates, Doctor of Philosophy Vanderbilt University 2007 - 2009
Master of Science, Masters University of Madras 1999 - 2003
Bachelor of Engineering, Bachelors, Electronics Engineering The University of Texas at Dallas
Skills:
Cmos
Simulations
Circuit Design
Analog
Cadence Virtuoso
Electrical Engineering
Testing
Semiconductor Device
Vlsi
Spice
Mixed Signal
Vhdl
Linux
Rf Design
Physics
Analog Circuit Design
Scripting
Programming Languages
Operating Systems
Databases
Rf
Cadence
Characterization
Analog and Digital Circuit Design
Reliability of Semi Conductors
Modelling of Electronic Circuits
Semiconductors
Interests:
Children
Economic Empowerment
Education
Poverty Alleviation
Science and Technology
Health
Srikanth Jagannathan Photo 2

Principal Engineer

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Location:
Austin, TX
Work:

Principal Engineer
Srikanth Jagannathan Photo 3

Principal Engineer

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Location:
Austin, TX
Work:

Principal Engineer
Srikanth Jagannathan Photo 4

Srikanth Jagannathan Nashville, TN

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Work:
TID Degradation

2013 to 2000
TID Degradation

2013 to 2000
Vanderbilt University

Jan 2011 to 2000
Vanderbilt University

Jun 2012 to Jan 2013
Characterization of Single Event Transients (SETs) in Digital Circuits

Jun 2009 to Jan 2012
CMOS Technology

2012 to 2012
CMOS Technology

2012 to 2012
CMOS Technology

2011 to 2011
Modeling of Charge Collection

Apr 2010 to Aug 2010
Neutrons, Internship
Analog Behavioral Modeling for Voltage Feedback Operational Amplifier, Vanderbilt University

Aug 2007 to Jun 2009
Education:
Vanderbilt University
Jun 2009
M.S in Electrical Engineering
University of Madras
Chennai, Tamil Nadu
Jun 2003
B.E. in Electrical & Electronics Engineering
Vanderbilt University
Ph.D. in Electrical Engineering

Publications

Us Patents

Differential Input Receiver Circuit Testing With A Loopback Circuit

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US Patent:
20230033973, Feb 2, 2023
Filed:
Jul 20, 2022
Appl. No.:
17/813774
Inventors:
- Austin TX, US
Srikanth Jagannathan - Austin TX, US
Frederic Benoist - Saint Paul de Vence, FR
International Classification:
H04B 1/10
H03F 3/45
H04B 1/16
H04L 25/02
Abstract:
A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.

Glitch Profiling In An Integrated Circuit

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US Patent:
20200402602, Dec 24, 2020
Filed:
Jun 18, 2019
Appl. No.:
16/444739
Inventors:
- AUSTIN TX, US
Srikanth Jagannathan - Austin TX, US
International Classification:
G11C 29/02
G11C 7/10
G01R 31/3193
Abstract:
A circuit includes a glitch measurement circuit and a glitch profile circuit. The glitch measurement circuit includes a first comparator to compare a glitch in a power supply voltage to a first threshold voltage, a first counter to generate a first count indicative of a time duration the first comparator indicates that the glitch trips the first threshold voltage, a second comparator to compare the glitch in the power supply voltage to a second threshold voltage different than the first threshold voltage, and a second counter to generate a second count indicative of a time duration the second comparator indicates that the glitch trips the second threshold voltage. The glitch profile circuitry utilizes the first count and the second count to generate a multi-voltage profile of the glitch, wherein the multi-voltage profile includes indications of the time durations indicated by the first count and the second count.

Low Power Mode Testing In An Integrated Circuit

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US Patent:
20200284830, Sep 10, 2020
Filed:
Mar 5, 2019
Appl. No.:
16/292654
Inventors:
- Austin TX, US
Srikanth JAGANNATHAN - Austin TX, US
Thomas Henry LUEDEKE - Oberbergkirchen, DE
Venkannababu AMBATI - Austin TX, US
Mark Shelton CINQUE - Austin TX, US
Joseph Rollin WRIGHT - Round Rock TX, US
International Classification:
G01R 31/28
Abstract:
An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

Analog To Digital Converter

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US Patent:
20200266825, Aug 20, 2020
Filed:
Feb 14, 2019
Appl. No.:
16/275647
Inventors:
- Austin TX, US
Srikanth JAGANNATHAN - Austin TX, US
George Rogers KUNNEN - Chandler AZ, US
International Classification:
H03M 1/36
Abstract:
An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.

Sram Based Physically Unclonable Function And Method For Generating A Puf Response

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US Patent:
20200243122, Jul 30, 2020
Filed:
Jan 29, 2019
Appl. No.:
16/260751
Inventors:
- Austin TX, US
SRIKANTH JAGANNATHAN - Austin TX, US
International Classification:
G11C 7/24
G11C 11/419
G11C 11/418
G11C 29/02
H04L 9/32
Abstract:
A data processing system includes an SRAM array, wherein the plurality of SRAM cells provide a physically unclonable function (PUF). A PUF evaluation engine includes a selection circuit for selecting one or more word lines coupled to the plurality of SRAM cells in response to a challenge, and a cross-coupled latch coupled to two bit lines corresponding to two different SRAM cells of the plurality of SRAM cells. The cross-coupled latch is configured to provide one of two 2-bit values depending on which of the two bit lines discharges faster upon the two different SRAM cells being selected by the selection circuit, wherein the 2-bit value is part of a digital code provided in response to the challenge.

Embedded Continuity Test Circuit

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US Patent:
20200191862, Jun 18, 2020
Filed:
Dec 18, 2018
Appl. No.:
16/223329
Inventors:
- AUSTIN TX, US
Srikanth JAGANNATHAN - AUSTIN TX, US
Hector SANCHEZ - AUSTIN TX, US
International Classification:
G01R 31/28
Abstract:
An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.

Comparator Circuit With Feedback And Method Of Operation

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US Patent:
20200021279, Jan 16, 2020
Filed:
Jul 10, 2018
Appl. No.:
16/030945
Inventors:
- AUSTIN TX, US
SRIKANTH JAGANNATHAN - Austin TX, US
MANMOHAN RANA - Ghaziabad, IN
CARL CULSHAW - Wigan, GB
International Classification:
H03K 5/24
H03K 3/037
G01R 31/40
Abstract:
A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Amplifier With Hysteresis

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US Patent:
20190288654, Sep 19, 2019
Filed:
Mar 14, 2018
Appl. No.:
15/920743
Inventors:
- Austin TX, US
Srikanth Jagannathan - Austin TX, US
International Classification:
H03F 3/45
H03F 1/02
Abstract:
An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.
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Srikanth Jagannathan from Austin, TX, age ~43 Get Report