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Srikant Sridevan

from Rancho Palos Verdes, CA
Age ~53
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Also known as:
Srikant N
Phone and address:
4818 Elkridge Dr, Palos Verdes Estates, CA 90275
(310) 542-8620
Related to:
Lee Price, 76Tonya Price, 55Stephen Price, 65Elmer Helmig, 73Beverly Rice, 83
Connected to:
Anupama Sridharan, 47Anurag M Sridharan, 36Aravind Sridharan, 30Aruna Sridharan, 28Ashok Sridharan, 42Bhargavi Sridhar, 35Hari Sridharan, 37Kalyani Sridhar, 46Kavitha Sridharan, 48Leela Sridharan, 60

Srikant Sridevan Phones & Addresses

  • 4818 Elkridge Dr, Rch Palos Vrd, CA 90275 (310) 542-8620
  • Rancho Palos Verdes, CA
  • 2311 Mathews Ave, Redondo Beach, CA 90278
  • 205 Via Riviera, Redondo Beach, CA 90277
  • El Segundo, CA
  • Raleigh, NC
  • Los Angeles, CA
  • 2311 Mathews Ave UNIT A, Redondo Beach, CA 90278

Work

Company: Bank of america Nov 2011 Position: Senior vice president

Education

Degree: Master of Business Administration, Masters School / High School: Ucla Anderson School of Management 2004 to 2007

Skills

Finance • Forecasting • Analytics • Risk Management • Management • Financial Modeling • Banking • Analysis • Credit • Project Planning • Financial Analysis • Credit Risk • Mortgage Banking • Strategic Financial Planning • Portfolio Management • Team Leadership • Financial Planning

Languages

Tamil • Hindi

Interests

Children • Education

Industries

Financial Services

Resumes

Resumes

Srikant Sridevan Photo 1

Senior Vice President

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Location:
Los Angeles, CA
Industry:
Financial Services
Work:
Bank of America
Senior Vice President
Bank of America Apr 2009 - Nov 2011
Vice President
Bank of America May 2008 - Apr 2009
1St Vice President, Finance
Bank of America Jun 2006 - May 2008
Vice President, Finance
International Rectifier 1998 - 2006
Design Manager
Education:
Ucla Anderson School of Management 2004 - 2007
Master of Business Administration, Masters North Carolina State University 1992 - 1998
Doctorates, Doctor of Philosophy Indian Institute of Technology, Madras 1988 - 1992
Bachelors, Bachelor of Technology
Skills:
Finance
Forecasting
Analytics
Risk Management
Management
Financial Modeling
Banking
Analysis
Credit
Project Planning
Financial Analysis
Credit Risk
Mortgage Banking
Strategic Financial Planning
Portfolio Management
Team Leadership
Financial Planning
Interests:
Children
Education
Languages:
Tamil
Hindi

Publications

Us Patents

Angle Implant Process For Cellular Deep Trench Sidewall Doping

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US Patent:
6509240, Jan 21, 2003
Filed:
May 10, 2001
Appl. No.:
09/852579
Inventors:
Liping Ren - Los Angeles CA
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 21336
US Classification:
438302, 438700
Abstract:
A process is described for making a superjunction semiconductor device, a large number of symmetrically spaced trenches penetrate the N epitaxial layer of silicon atop an N body to a depth of 35 to 40 microns. The wells have a circular cross-section and a diameter of about 9 microns. The trench walls are implanted by an ion implant beam of boron which is at a slight angle to the axis of the trenches. The wafer is intermittently or continuously rotated about an axis less than 90Â to its surface to cause skewing of the implant beam and more uniform distribution of boron ions over the interior surfaces of the trenches.

Superjunction Device With Self Compensated Trench Walls

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US Patent:
6512267, Jan 28, 2003
Filed:
Apr 12, 2001
Appl. No.:
09/834115
Inventors:
Daniel M. Kinzer - El Segundo CA
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 2978
US Classification:
257335, 257339, 257342
Abstract:
A superjunction device has a large number of symmetrically located vertical circular wells in a high resistivity silicon substrate. A plurality of alternate opposite conductivity N and P stripes or nodes are formed along the length of the walls of each of the wells. Each of the nodes faces an opposite concentration type node in an adjacent well. A DMOS gate structure is connected to the tops of the N stripes. The nodes have a depth and concentration to cause full depletion of all nodes during reverse bias. Current flows through the relatively low resistance N stripes when its gate is turned on. A conventional termination such as a diffused ring or rings can surround the active area of all cells and is formed in the high resistivity substrate.

Polysilicon Fet Built On Silicon Carbide Diode Substrate

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US Patent:
6552363, Apr 22, 2003
Filed:
Sep 18, 2001
Appl. No.:
09/955655
Inventors:
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 310312
US Classification:
257 77
Abstract:
A polysilicon FET is built atop a SiC diode to form a MOSgated device. The polysilicon FET includes an invertible layer of polysilicon atop the surface of a SiC diode which has spaced diode diffusions. A MOSgate is formed on the polysilicon layer and the energization of the gate causes an inversion channel in the invertible layer to form a majority carrier conduction path from a top source electrode to a bottom drain electrode. Forward voltage is blocked in part by the polysilicon FET and in larger part by the depletion of the silicon carbide area between the spaced diode diffusions.

High Voltage Vertical Conduction Superjunction Semiconductor Device

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US Patent:
6608350, Aug 19, 2003
Filed:
Dec 7, 2000
Appl. No.:
09/732401
Inventors:
Daniel M. Kinzer - El Segundo CA
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 2978
US Classification:
257341, 257331, 257339
Abstract:
A high voltage vertical conduction semiconductor device has a plurality of deep trenches or holes in a lightly doped body of one conductivity type. A diffusion of the other conductivity type is formed in the trench walls to a depth and a concentration which matches that of the body so that, under reverse blocking, both regions fully deplete. The elongated trench or hole is filled with a dielectric which may be a composite of nitride and oxide layers having a lateral dimension change matched to that of the silicon. The filler may also be a highly resistive SIPOS which permits leakage current flow from source to drain to ensure a uniform electric field distribution along the length of the trench during blocking.

Method Of Preparing Polysilicon Fet Built On Silicon Carbide Diode Substrate

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US Patent:
6727128, Apr 27, 2004
Filed:
Feb 24, 2003
Appl. No.:
10/372550
Inventors:
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 218234
US Classification:
438197, 438590, 257 77
Abstract:
A polysilicon FET is built atop a SiC diode to form a MOSgated device. The polysilicon FET includes an invertible layer of polysilicon atop the surface of a SiC diode which has spaced diode diffusions. A MOSgate is formed on the polysilicon layer and the energization of the gate causes an inversion channel in the invertible layer to form a majority carrier conduction path from a top source electrode to a bottom drain electrode. Forward voltage is blocked in part by the polysilicon FET and in larger part by the depletion of the silicon carbide area between the spaced diode diffusions.

Lateral Conduction Superjunction Semiconductor Device

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US Patent:
6787872, Sep 7, 2004
Filed:
Jun 26, 2001
Appl. No.:
09/891727
Inventors:
Daniel M. Kinzer - El Segundo CA
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 2358
US Classification:
257492, 257493
Abstract:
A lateral conduction superjunction semiconductor device has a plurality of spaced vertical trenches in a junction receiving layer of P silicon. An N diffusion lines the walls of the trench and the concentration and thickness of the N diffusion and P mesas are arranged to deplete fully in reverse blocking operation. A MOSgate structure is connected at one end of the trenches and a drain is connected at its other end. An N further layer or an insulation oxide layer may be interposed between a P substrate and the P junction receiving layer.

Trench Fill Process

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US Patent:
6812525, Nov 2, 2004
Filed:
Jun 18, 2003
Appl. No.:
10/465496
Inventors:
Igor Bul - Sherman Oaks CA
Srikant Sridevan - Redondo Beach CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 2976
US Classification:
257341, 257510, 257513, 257520
Abstract:
A process for insulating the interior of the trenches of trench type MOSgated devices in which a capping oxide is formed over the top of the trenches to span approximately a 3 micron gap and then reflowing the oxide at 1050Â C. in pure O to flush air out of the trenches and leaving an at least partially evacuated sealed volume in each of the trenches.

Bidirectional Shallow Trench Superjunction Device With Resurf Region

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US Patent:
6835993, Dec 28, 2004
Filed:
Aug 26, 2003
Appl. No.:
10/649929
Inventors:
Srikant Sridevan - Redondo Beach CA
Daniel M. Kinzer - El Segundo CA
Assignee:
International Rectifier Corporation - El Segundo CA
International Classification:
H01L 2358
US Classification:
257492, 257330
Abstract:
A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.
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Srikant Sridevan from Rancho Palos Verdes, CA, age ~53 Get Report