Srijit Mukherjee

20140070320, Mar 13, 2014

Sep 7, 2012

13/606768

Srijit Mukherjee - Hillsboro OR, US
Christopher J. Wiegand - Portland OR, US
Mark Y. Liu - West Linn OR, US
Michael L. Hattendorf - Portland OR, US

H01L 27/088
H01L 29/66

257368, 438585

Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

20230042218, Feb 9, 2023

Oct 17, 2022

17/967511

- Santa Clara CA, US
Srijit MUKHERJEE - Hillsboro OR, US
Vinay BHAGWAT - Hillsboro OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 21/8238
H01L 27/092
H01L 29/08
H01L 23/522
H01L 29/51
H01L 21/8234
H01L 23/528
H01L 21/768
H01L 49/02
H01L 21/28
H01L 29/78
H01L 21/311
H01L 27/11
H01L 29/417
H01L 23/532
H01L 21/033
H01L 21/308
H01L 21/762
H01L 29/66
H01L 21/285

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

20210408258, Dec 30, 2021

Jun 25, 2020

16/912118

- Santa Clara CA, US
Glenn A. GLASS - Portland OR, US
Thomas T. TROEGER - Portland OR, US
Suresh VISHWANATH - Portland OR, US
Jitendra Kumar JHA - Hillsboro OR, US
John F. RICHARDS - Portland OR, US
Anand S. MURTHY - Portland OR, US
Srijit MUKHERJEE - Portland OR, US

H01L 29/45
H01L 29/78
H01L 29/08
H01L 29/161
H01L 29/49
H01L 21/28
H01L 21/285
H01L 29/66

Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi.

20210167019, Jun 3, 2021

Sep 1, 2017

16/636315

- Santa Clara CA, US
Srijit Mukherjee - Portland OR, US
Jason Farmer - Hillsboro OR, US
Chandan Ganpule - Portland OR, US
Julia Lin - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 23/532
H01L 21/768

Provided herein are metal interconnects that may include a cobalt alloy, a nickel alloy, or nickel. Also provided herein are methods of making metal interconnects. The metal interconnects may include a barrier and/or adhesion layer, a seed layer, a fill material, a cap, or a combination thereof, and at least one of the barrier and/or adhesion layer, the seed layer, the fill material, or the cap may include a cobalt alloy, a nickel alloy, nickel, or a combination thereof.

20210043520, Feb 11, 2021

Oct 12, 2020

17/068121

- Santa Clara CA, US
Srijit MUKHERJEE - Hillsboro OR, US
Vinay BHAGWAT - Hillsboro OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 21/8238
H01L 49/02
H01L 21/762
H01L 21/8234
H01L 21/311
H01L 29/08
H01L 27/11
H01L 29/78
H01L 29/66
H01L 21/308
H01L 27/092
H01L 29/51
H01L 21/285
H01L 21/28
H01L 21/033
H01L 21/768
H01L 23/532
H01L 23/522
H01L 23/528
H01L 29/417

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

20200013680, Jan 9, 2020

Jul 19, 2019

16/516693

- Santa Clara CA, US
Srijit MUKHERJEE - Hillsboro OR, US
Vinay BHAGWAT - Hillsboro OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 21/8238
H01L 49/02
H01L 21/762
H01L 21/8234
H01L 21/311
H01L 29/08
H01L 27/11
H01L 29/78
H01L 29/66
H01L 21/308
H01L 27/092
H01L 29/51
H01L 21/285
H01L 21/28
H01L 21/033
H01L 21/768
H01L 23/532
H01L 23/522
H01L 23/528

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

20190164846, May 30, 2019

Dec 30, 2017

15/859357

- Santa Clara CA, US
Srijit MUKHERJEE - Hillsboro OR, US
Vinay BHAGWAT - Hillsboro OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 21/8238
H01L 29/78
H01L 21/762
H01L 21/8234
H01L 21/311
H01L 29/08
H01L 27/11
H01L 29/66
H01L 21/308
H01L 27/092
H01L 29/51
H01L 21/285
H01L 21/28
H01L 21/033
H01L 21/768
H01L 23/532
H01L 23/522
H01L 23/528
H01L 49/02

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

20180151423, May 31, 2018

Jun 3, 2015

15/570857

Christopher J. Jezewski - Hillsboro OR, US
Srijit Mukherjee - Hillsboro OR, US
Daniel B. Bergstrom - Lake Oswego OR, US
Tejaswi K. Indukuri - Portland OR, US
Flavio Griggio - Portland OR, US
Ramanan V. Chebiam - Hillsboro OR, US
James S. Clarke - Portland OR, US

H01L 21/768
H01L 23/532

In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.