Resumes
Resumes
Sri Manjunath
View pagePosition:
Teaching Assistant at California State University, Sacramento
Location:
Sacramento, California Area
Industry:
Semiconductors
Work:
California State University, Sacramento since Jan 2009
Teaching Assistant
Bosch Apr 2008 - Aug 2008
Embedded System Engineer
Electronics and Radar development Establishment Nov 2007 - Mar 2008
Research Fellow
Teaching Assistant
Bosch Apr 2008 - Aug 2008
Embedded System Engineer
Electronics and Radar development Establishment Nov 2007 - Mar 2008
Research Fellow
Education:
California State University-Sacramento 2008 - 2010
Master of Science, MicroelectronicsANALOG AND MIXED SIGNAL DESIGN PROJECTS: ÃÂâÃÂÃÂÃÂâ CMOS 2 stage Miller Operational Amplifier Design (Mentor IC design Tool). ÃÂâÃÂÃÂÃÂâ Design of Differential CMOS Operational Amplifier with input referred offset voltage less than 5mV (Mentor IC design Tool). ÃÂâÃÂÃÂÃÂâ Design and Layout of Current Mode Logic (CML) Buffer with 50ÃÂÃÂÃÂé Output Pad Driver (Mentor IC design Tool). ÃÂâÃÂÃÂÃÂâ Design and simulate a CMOS latching comparator (OrCad Pspice). ÃÂâÃÂÃÂÃÂâ Matlab behavioral model of pipelined ADC (MATLAB 2007). DIGITAL DESIGN PROJECTS: ÃÂâÃÂÃÂÃÂâ Parallel-to-Serial Transmit Interface design (Verilog in Synopsis VCS). ÃÂâÃÂÃÂÃÂâ Cache-Memory Subsystem Design (Verilog). ÃÂâÃÂÃÂÃÂâ ADC-SRAM Interface DesignÃÂâÃÂÃÂÃÂâ Flash-SRAM Interface Design (Verilog in Xilinx ISE and Modelsim). ÃÂâÃÂÃÂÃÂâ Verilog / VHDL logic design hardware projects (Xilinx Virtex 5 FPGA, Verilog in Xilinx ISE and Modelsim). ÃÂâÃÂÃÂÃÂâ Design of Vending Machine Controller in CMOS level (Cadence and LEDIT). GRADUATE PROJECT: A Novel Residue Stage Architecture for Pipelined ADC (Under Progress). Visvesvaraya Technological University 2003 - 2007
2007, Electronics and Communication engineeringProject: Spread spectrum technique for voice communication. (Sponsored by: Karnataka State council for Science and Technology(KSCST), Indian Institute of Science(IISc), Bangalore, India (http://www.kscst.iisc.ernet.in/) Courses: VLSI design Circuit analysis and design RF and Microwave circuit design Advanced analog and digital communication Operating system principles Advanced C and C++ programming California State University-Sacramento
MS, Electrical and Electronics Engineering Dr.Ambedkar Institute of technology
B.E, Electronics and Communication Engineering
Master of Science, MicroelectronicsANALOG AND MIXED SIGNAL DESIGN PROJECTS: ÃÂâÃÂÃÂÃÂâ CMOS 2 stage Miller Operational Amplifier Design (Mentor IC design Tool). ÃÂâÃÂÃÂÃÂâ Design of Differential CMOS Operational Amplifier with input referred offset voltage less than 5mV (Mentor IC design Tool). ÃÂâÃÂÃÂÃÂâ Design and Layout of Current Mode Logic (CML) Buffer with 50ÃÂÃÂÃÂé Output Pad Driver (Mentor IC design Tool). ÃÂâÃÂÃÂÃÂâ Design and simulate a CMOS latching comparator (OrCad Pspice). ÃÂâÃÂÃÂÃÂâ Matlab behavioral model of pipelined ADC (MATLAB 2007). DIGITAL DESIGN PROJECTS: ÃÂâÃÂÃÂÃÂâ Parallel-to-Serial Transmit Interface design (Verilog in Synopsis VCS). ÃÂâÃÂÃÂÃÂâ Cache-Memory Subsystem Design (Verilog). ÃÂâÃÂÃÂÃÂâ ADC-SRAM Interface DesignÃÂâÃÂÃÂÃÂâ Flash-SRAM Interface Design (Verilog in Xilinx ISE and Modelsim). ÃÂâÃÂÃÂÃÂâ Verilog / VHDL logic design hardware projects (Xilinx Virtex 5 FPGA, Verilog in Xilinx ISE and Modelsim). ÃÂâÃÂÃÂÃÂâ Design of Vending Machine Controller in CMOS level (Cadence and LEDIT). GRADUATE PROJECT: A Novel Residue Stage Architecture for Pipelined ADC (Under Progress). Visvesvaraya Technological University 2003 - 2007
2007, Electronics and Communication engineeringProject: Spread spectrum technique for voice communication. (Sponsored by: Karnataka State council for Science and Technology(KSCST), Indian Institute of Science(IISc), Bangalore, India (http://www.kscst.iisc.ernet.in/) Courses: VLSI design Circuit analysis and design RF and Microwave circuit design Advanced analog and digital communication Operating system principles Advanced C and C++ programming California State University-Sacramento
MS, Electrical and Electronics Engineering Dr.Ambedkar Institute of technology
B.E, Electronics and Communication Engineering
Skills:
Digital system design and verification
Hierarchical digital design using verilog
VHDL
Static timing analysis (Synopsys DC and PT)
Low power analog circuit design (ADC
PLL
Opamps
high speed comparators
Current mode logic(CML)
Analog layouts : using Cadance and Mentor IC design tool)
Computer architecture(cache design
PCI architecture)
Hierarchical digital design using verilog
VHDL
Static timing analysis (Synopsys DC and PT)
Low power analog circuit design (ADC
PLL
Opamps
high speed comparators
Current mode logic(CML)
Analog layouts : using Cadance and Mentor IC design tool)
Computer architecture(cache design
PCI architecture)
Interests:
Analog and Mixed Signal Design, Low power digital circuit design, Layouts, Data converters, Design Automation.
Sri Manjunath Sacramento, CA
View pageWork:
BOSCH
Aug 2006 to Aug 2008
Design and Test Engineer
LRDE, India
Jan 2006 to Jun 2006
Research Fellow (Intern)
Aug 2006 to Aug 2008
Design and Test Engineer
LRDE, India
Jan 2006 to Jun 2006
Research Fellow (Intern)
Education:
Visveswarayya Technological University
Jun 2006
Bachelor of Engineering in Electronics and Communication Engineering
California State University
Sacramento, CA
Master of Science in Electrical and Electronic Engineering
Jun 2006
Bachelor of Engineering in Electronics and Communication Engineering
California State University
Sacramento, CA
Master of Science in Electrical and Electronic Engineering
Skills:
C, C++, Verilog, UNIX, Linux, ASIC, Digtal IC design and verification, perl, Tcl