Search

Soraya A Ghiasi

from Boulder, CO
Age ~55
Get Report
Also known as:
Soraya N Ghiasi, Soraya N Seidl, Soraya Chiasi
Phone and address:
4163 Nevis St, Boulder, CO 80301
(303) 726-4038
Related to:
Mary C Kreutzfeldt, 74Roger Sheng, 37Shu J Sun, 56Ta I Lin, 65
Connected to:
Mayshan Ghiassi, 45Sarah L Ghiazza, 44Persida I Ghibilic, 55Alexander B Ghibu, 129Elena Ghibus, 49Daniel Ghica, 45Paul L Ghica, 42Glenn D Ghidaleson, 72Claudia Ghidella, 67Anna M Ghidina, 45

Soraya Ghiasi Phones & Addresses

  • 4163 Nevis St, Boulder, CO 80301 (303) 726-4038
  • 4725 Shoup Pl, Boulder, CO 80303 (720) 379-4523
  • Arvada, CO
  • 13314 Council Bluff Dr, Austin, TX 78727 (512) 388-4349
  • 1034 Grant St, Longmont, CO 80501 (303) 682-5850 (303) 682-5848
  • Carson, NM
  • 4163 Nevis St, Boulder, CO 80301

Work

Position: Student

Education

Degree: Associate degree or higher

Resumes

Resumes

Soraya Ghiasi Photo 1

Research Staff Member At Ibm

View page
Position:
Research Staff Member at IBM
Location:
Greater Denver Area
Industry:
Computer Hardware
Work:
IBM
Research Staff Member
IBM 2004 - 2009
Research
University of Colorado at Boulder 1999 - 2004
researcher/grad student
Clue Computing 1997 - 1999
system administration contractor
Education:
University of Colorado at Boulder 1998 - 2004
Soraya Ghiasi Photo 2

Soraya Ghiasi

View page

Publications

Us Patents

Scheduling Processor Voltages And Frequencies Based On Performance Prediction And Power Constraints

View page
US Patent:
7386739, Jun 10, 2008
Filed:
May 3, 2005
Appl. No.:
11/120899
Inventors:
Soraya Ghiasi - Austin TX, US
Ramakrishna Kotla - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.

Sensor Subset Selection For Reduced Bandwidth And Computation Requirements

View page
US Patent:
7502705, Mar 10, 2009
Filed:
May 29, 2007
Appl. No.:
11/754468
Inventors:
Andreas Bieswanger - Baden-Württemberg, DE
Michael S. Floyd - Austin TX, US
Andrew J. Geissler - Pflugerville TX, US
Soraya Ghiasi - Austin TX, US
Hye-Young McCreary - Liberty Hill TX, US
Guillermo J. Silva - Austin TX, US
Malcolm S. Ware - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 19/00
US Classification:
702116
Abstract:
A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.

Weighted Event Counting System And Method For Processor Performance Measurements

View page
US Patent:
7533003, May 12, 2009
Filed:
Dec 5, 2007
Appl. No.:
11/951310
Inventors:
Michael S. Floyd - Austin TX, US
Soraya Ghiasi - Austin TX, US
Karthick Rajamani - Austin TX, US
Juan C. Rubio - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01F 19/00
US Classification:
702186, 709238
Abstract:
A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Processing Performance Improvement Using Activity Factor Headroom

View page
US Patent:
7681054, Mar 16, 2010
Filed:
Oct 3, 2006
Appl. No.:
11/538131
Inventors:
Soraya Ghiasi - Austin TX, US
Thomas Walter Keller - Austin TX, US
Karthick Rajamani - Austin TX, US
Juan C. Rubio - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/32
G06F 1/26
US Classification:
713320, 713300, 713323, 320127
Abstract:
Processing system performance is improved while meeting power management constraints in a processing system by using activity factor headroom estimation. The method and system estimate the power consumption of the system from a model that relates measured activities at a present operating point to power consumption for any available operating point of one or more processors in the system. The method then chooses the operating point(s) with the highest performance among the available operating points that will still meet budgetary constraints or specific thresholds of power consumption. The budgetary constraints or specific thresholds may be dynamically adjusted, and the method will update the operating point(s) to maintain safe operation and maximize performance. The method provides the best performance for the executing workload while ensuring safe operation.

Unified Management Of Power, Performance, And Thermals In Computer Systems

View page
US Patent:
7908493, Mar 15, 2011
Filed:
Jun 6, 2007
Appl. No.:
11/758798
Inventors:
Andreas Bieswanger - Ehningen, DE
Michael S. Floyd - Cedar Park TX, US
Soraya Ghiasi - Austin TX, US
Steven P. Hartman - Round Rock TX, US
Hye-Young McCreary - Liberty Hill TX, US
Karthick Rajamani - Austin TX, US
Juan C. Rubio - Austin TX, US
Malcolm S. Ware - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/32
US Classification:
713300, 310320
Abstract:
A mechanism is provided for unified management of power, performance, and thermals in computer systems. This mechanism incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The mechanism employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The mechanism provides interfaces for user-level interaction. The mechanism also employs methods to address power/thermal concerns at multiple timescales. In addition, the mechanism improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.

Tracking Thermal Mini-Cycle Stress

View page
US Patent:
7917328, Mar 29, 2011
Filed:
Aug 20, 2008
Appl. No.:
12/194606
Inventors:
Jon A. Casey - Poughkeepsie NY, US
Michael S. Floyd - Cedar Park TX, US
Soraya Ghiasi - Boulder CO, US
Kenneth C. Marston - Poughquag NY, US
Jennifer V. Muncy - Ridgefield CT, US
Malcom S. Ware - Austin TX, US
Roger D. Weekly - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 19/00
US Classification:
702132, 374 10
Abstract:
Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.

Scheduling Processor Voltages And Frequencies Based On Performance Prediction And Power Constraints

View page
US Patent:
7921313, Apr 5, 2011
Filed:
Apr 17, 2008
Appl. No.:
12/105206
Inventors:
Soraya Ghiasi - Austin TX, US
Ramakrishna Kotla - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/26
US Classification:
713300, 713320
Abstract:
A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.

Sensor Subset Selection For Reduced Bandwidth And Computation Requirements

View page
US Patent:
8032334, Oct 4, 2011
Filed:
Dec 22, 2008
Appl. No.:
12/342054
Inventors:
Andreas Bieswanger - Ehningen, DE
Michael S. Floyd - Austin TX, US
Andrew J. Geissler - Pflugerville TX, US
Soraya Ghiasi - Austin TX, US
Hye-Young McCreary - Liberty Hill TX, US
Guillermo J. Silva - Austin TX, US
Malcolm S. Ware - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
G06F 19/00
US Classification:
702188, 700 74
Abstract:
A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.
Control profile
Soraya A Ghiasi from Boulder, CO, age ~55 Get Report