Sompong Paul Olarig

5881293, Mar 9, 1999

Aug 20, 1996

8/699921

Sompong Paul Olarig - Cypress TX
Dale J. Mayer - Houston TX
William F. Whiteman - Cypress TX

Compaq Computer Corporation - Houston TX

G06F 1300

395733

A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

6360333, Mar 19, 2002

Nov 19, 1998

09/196463

Kenneth A. Jansen - Spring TX
Sompong P. Olarig - Cypress TX
John E. Jenne - Houston TX

Compaq Computer Corporation - Houston TX

G06F 1100

714 25, 709202

A multiprocessor computer includes a fault detection scheme which detects and identifies the failure of one of the processors. Each processor is assigned a write location, which may be a unique register. During normal computer operation, each processor intermittently performs a test and stores the results of the test in the assigned write location. The stored results are compared to expected results, and an error signal is generated if the stored results differ from the expected results to indicate that one of the processors has failed.

6363449, Mar 26, 2002

Mar 29, 1999

09/280313

Chi Kim Sides - Spring TX
Michael F. Angelo - Houston TX
Sompong P. Olarig - Cypress TX

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1300

710129, 34031001

A method and system of interchassis and intrachassis computer component command and control. The existing power rail is used for network connectivity for intrachassis command and control. An existing common power mains can be used for interchassis command and control. Further, a protocol, for example, the Consumer Electronic Bus (CEBus) protocol (or a CEBus protocol modified for the particular power rail) can be used to provide interchassis and intrachassis platform management functionality. This management functionality is similar to that provided by the proposed Intelligent Platform Management Interface (IPMI) specification. A chassis bridge controller is used to interface the intrachassis power rail command and control infrastructure to an exterior network. External systems (interchassis communications) can communicate to the bridge via the particular protocol over an existing common power mains as a secondary channel exterior network. However, the management functionality is implemented intrachassis, that is, it is applied to the internal components of the machine.

6370656, Apr 9, 2002

Nov 19, 1998

09/195922

Sompong P. Olarig - Cypress TX
John E. Jenne - Houston TX

Compaq Information Technologies, Group L. P. - Houston TX

G06F 1100

714 23, 709201

A computer system comprises a variety of components transmitting variable-rate heartbeats to a heartbeat monitor, each heartbeat indicating that the component is functioning properly. In addition, selected components serve as proxies by transmitting heartbeats to indicate that another component is functioning properly. In the preferred embodiment, one or more central processing units (CPUs) transmit heartbeats to indicate proper CPU functioning, while a bridge logic device and a network interface card (NIC) transmit heartbeats as proxies for a memory device and an external computer system, respectively. The heartbeat monitor is capable of determining initial heart rates for each component and is further capable of adaptively varying the heart rates thereafter. If the age of the heartbeat sender is relatively young, then a relatively slow heart rate is specified. Faster heart rates are specified for older components.

6370657, Apr 9, 2002

Nov 19, 1998

09/196264

Kenneth A. Jansen - Spring TX
Sompong P. Olarig - Cypress TX
John E. Jenne - Houston TX

Compaq Computer Corporation - Houston TX

G06F 1100

714 23, 714 43

A scheme may be used to remove or replace a processor in a multiprocessor computer without the need for turning the computer off to replace the processor. In this scheme, the bus to which the processor is coupled is identified so that all processors coupled to the bus may be placed in sleep mode. This act does not alter the normal operation of processors that may be coupled to another bus. Once the processors are in sleep mode, the processor may be removed or replaced. Afterward, all processors may be returned to normal operation.

6418533, Jul 9, 2002

Aug 29, 1997

08/927096

Michael F. Angelo - Houston TX
Sompong P. Olarig - Cypress TX

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1264

713202, 713 1, 713 2, 713100, 713200

A computer security system whereby access is controlled by remote enablement or disablement. The system can be coupled with third-party products to accommodate satellite transmissions for long-distance access control.

6430702, Aug 6, 2002

Nov 15, 2000

09/713738

Paul A. Santeler - Cypress TX
Kenneth A. Jansen - Spring TX
Sompong P. Olarig - Cypress TX

Compaq Computer Corporation - Houston TX

G06F 1100

714 6

A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

6449677, Sep 10, 2002

Mar 11, 1999

09/266356

Sompong Paul Olarig - Cypress TX
Thomas R. Seeman - Tomball TX
Kenneth Jansen - Spring TX
Dwight D. Riley - Houston TX

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1338

710305, 710307, 710314, 710315, 710309

A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave in a predictable manner with current devices.