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Soheil Gharahi

from Austin, TX
Age ~34
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Related to:
Fatemeh Moradian, 60Samaneh Gharahi, 38Sami GharahiChitza GharahEbrahim Gharahi, 66Kamal Gharahi, 75
Connected to:
Namir D Gharaibeh, 53Nasir G Gharaibeh, 57Editte Gharakhanian, 63Karmen Gharakhanian, 64Hrire Gharapetian, 80Patrick Gharassimian, 39Manoj Gharat, 48Pranay Gharat, 39Pranjali P Gharat, 39Emad E Gharavi, 57

Soheil Gharahi Phones & Addresses

  • Austin, TX
  • Sunnyvale, CA
  • Coppell, TX

Work

Company: Intel corporation Apr 2014 Position: Pre-silicon validation intern

Education

School / High School: The University of Texas at Austin- Austin, TX Dec 2012 Specialities: Bachelors in Electrical and Computer Engineering

Resumes

Resumes

Soheil Gharahi Photo 1

Soheil Gharahi Austin, TX

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Work:
Intel Corporation

Apr 2014 to 2000
Pre-silicon Validation Intern
Intel Corporation

Dec 2012 to Apr 2014
Product Development Engineer (Full time)
Intel Corporation

Feb 2012 to Dec 2012
Product Development Engineering Intern
UT Microelectronics Research Center

May 2011 to Dec 2011
Research Intern
Education:
The University of Texas at Austin
Austin, TX
Dec 2012
Bachelors in Electrical and Computer Engineering
The University of Texas at Austin
Austin, TX
Apr 2000
Masters in Integrated Circuits and Systems

Publications

Us Patents

Coordinating Power Transitions Between A Smart Interconnect And Heterogeneous Components

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US Patent:
20210365273, Nov 25, 2021
Filed:
Aug 5, 2021
Appl. No.:
17/395313
Inventors:
- Shenzhen City, CN
Omar Mahmoud Afdal ALNAGGAR - Palo Alto CA, US
Myron O. SHAK - San Jose CA, US
Soheil GHARAHI - Mountain View CA, US
William KELSEY - San Francisco CA, US
Assignee:
North Sea Investment Co. Ltd. - Shenzhen City
International Classification:
G06F 9/445
G06F 21/57
G06F 1/26
G06F 13/42
G06F 1/24
G06F 21/81
Abstract:
Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.

Method For Creation Of Different Designs By Combining A Set Of Pre-Defined Disjoint Masks

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US Patent:
20210349392, Nov 11, 2021
Filed:
Dec 11, 2019
Appl. No.:
17/278226
Inventors:
- Futian District, Shenzhen City, CN
Soheil Gharahi - Santa Clara CA, US
Assignee:
North Sea Investment Company Ltd. - Shenzhen City
International Classification:
G03F 7/20
H01L 21/027
Abstract:
Described are methods for enabling the creation of multiple similar designs by utilizing sets of multiple, disjoint fabrication masks. A first set of device features may be formed from a material layer in a first portion of a die area of a semiconductor substrate based on a first photolithographic exposure. A second set of device features may be formed from the material layer in a second portion of the die area of the semiconductor substrate based on a second photolithographic exposure after the first photolithographic exposure. The first portion of the die area and the second portion of the die area may be non-overlapping.

Method And Apparatus For Dynamic Routing Using Heterogeneous And Disjoint Networks

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US Patent:
20210126641, Apr 29, 2021
Filed:
Jun 28, 2018
Appl. No.:
16/605733
Inventors:
- Shenzhen City, CN
Myron O. SHAK - Mountain View CA, US
Soheil GHARAHI - Mountain View CA, US
Assignee:
North Sea Investment Co. Ltd. - Shenzhen City
International Classification:
H03K 19/17736
H03H 11/02
Abstract:
Described are concepts related to the field of programmable interconnect substrates used in packaging electronics, and to stacked integrated circuits produced for application in low power and small form factor designs with fast prototyping and short mass-production cycle times. The concepts facilitate the dynamic reconfiguration of routing resources in the presence of an active system, and the tuning of routing paths to meet power and performance metrics.
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Soheil Gharahi from Austin, TX, age ~34 Get Report