Resumes
Resumes
Sivayya Ayinala Phones & Addresses
-
106 Whitley Dr, Austin, TX 78738 (972) 943-0777
-
3425 Grand Mesa Dr, Plano, TX 75025 (972) 943-0777
-
3801 Spring Creek Pkwy, Plano, TX 75023 (972) 943-0777
-
Beaverton, OR
-
106 Whitley Dr, Austin, TX 78738
Work
Position:
Executive, Administrative, and Managerial
Education
Degree:
High school graduate or higher
Publications
Us Patents
Multi-Threaded Dma
View pageUS Patent:
7761617, Jul 20, 2010
Filed:
Mar 17, 2005
Appl. No.:
11/082564
Inventors:
Franck Seigneret - Roquefort les pins, FR
Sivayya Ayinala - Plano TX, US
Nabil Khalifa - Saint Laurent du Van, FR
Praveen Kolli - Dallas TX, US
Prabha Atluri - Plano TX, US
Sivayya Ayinala - Plano TX, US
Nabil Khalifa - Saint Laurent du Van, FR
Praveen Kolli - Dallas TX, US
Prabha Atluri - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
G06F 13/00
G06F 13/00
US Classification:
710 22, 710 23, 710 24, 710 35
Abstract:
A direct memory access (DMA) circuit () includes a read port () and a write port (). The DMA circuit () is a multithreaded initiator with “m” threads on the read port () and “n” threads on the write port (). The DMA circuit () includes two decoupled read and write contexts and schedulers () that provide for more efficient buffering and pipelining. The schedulers () are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
Multi-Channel Dma With Shared Fifo
View pageUS Patent:
7373437, May 13, 2008
Filed:
Mar 15, 2005
Appl. No.:
11/080277
Inventors:
Franck Seigneret - Roquefort les pins, FR
Nabil Khalifa - Saint Laurent du Var, FR
Sivayya Ayinala - Plano TX, US
Praveen Kolli - Dallas TX, US
Nabil Khalifa - Saint Laurent du Var, FR
Sivayya Ayinala - Plano TX, US
Praveen Kolli - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
US Classification:
710 22, 710 26, 710308, 709212
Abstract:
A direct memory access (DMA) circuit () includes a read port () and a write port (). The DMA circuit () is a multithreaded initiator with “m” threads on the read port () and “n” threads on the write port (). The DMA circuit () includes a data FIFO () which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO () can also be allocated to a single channel if there is only one logical channel active. The FIFO () increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.
Apparatus And Method For Automatically Saving And Restoring Pad Configuration Registers Implemented In A Core Power Domain
View pageUS Patent:
8117428, Feb 14, 2012
Filed:
Jun 4, 2009
Appl. No.:
12/478715
Inventors:
Alain Breton - Saint Paul, FR
Christophe Vatinel - Mouans Sartoux, FR
Sivayya Venkata Ayinala - Plano TX, US
Christophe Vatinel - Mouans Sartoux, FR
Sivayya Venkata Ayinala - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 9/24
G06F 15/177
G06F 15/177
US Classification:
713 1, 713 2, 713320, 713323, 711100
Abstract:
According to various illustrative embodiments, an apparatus, system, and method for automatically saving and restoring pad configuration registers implemented in a core power domain are described. In one aspect, the apparatus comprises a save and restore logic component implemented in the core power domain and coupled to the pad configuration registers. The apparatus also comprises a memory instantiated in an always-on power domain and coupled to the save and restore logic component, the save and restore logic component implemented in the core power domain to automatically save the pad configuration registers in the memory in a pad configuration save process before a power supply to the core power domain is switched off and to automatically restore the pad configuration registers from the memory in a pad configuration restore process after the power supply to the core power domain is switched on.
Method And System For Reducing Power Consumption Of A Direct Memory Access Controller
View pageUS Patent:
20060179172, Aug 10, 2006
Filed:
Jan 28, 2005
Appl. No.:
11/045215
Inventors:
Sivayya Ayinala - Plano TX, US
Praveen Kolli - Dallas TX, US
Praveen Kolli - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
US Classification:
710022000
Abstract:
A method and system for reducing the power consumption of a direct memory access (DMA) controller. A preferred method, for example, comprises: queuing a first DMA request in a queue; responding to the first queued DMA request when the computer system resources necessary for a DMA transfer are available; and placing at least some components of the computer system into a reduced power consumption state when the computer system resources necessary for the DMA transfer are not available.
Datapath Circuitry For Math Operations Using Simd Pipelines
View pageUS Patent:
20210109761, Apr 15, 2021
Filed:
Oct 9, 2019
Appl. No.:
16/597625
Inventors:
- Cupertino CA, US
Robert D. Kenney - Austin TX, US
Terence M. Potter - Austin TX, US
Vinod Reddy Nalamalapu - Austin TX, US
Sivayya V. Ayinala - Austin TX, US
Robert D. Kenney - Austin TX, US
Terence M. Potter - Austin TX, US
Vinod Reddy Nalamalapu - Austin TX, US
Sivayya V. Ayinala - Austin TX, US
International Classification:
G06F 9/38
G06F 9/30
G06F 17/16
G06F 9/30
G06F 17/16
Abstract:
Techniques are disclosed relating to sharing operands among SIMD threads for a larger arithmetic operation. In some embodiments, a set of multiple hardware pipelines is configured to execute single-instruction multiple-data (SIMD) instructions for multiple threads in parallel, where ones of the hardware pipelines include execution circuitry configured to perform floating-point operations using one or more pipeline stages of the pipeline and first routing circuitry configured to select, from among thread-specific operands stored for the hardware pipeline and from one or more other pipelines in the set, a first input operand for an operation by the execution circuitry. In some embodiments, a device is configured to perform a mathematical operation on source input data structures stored across thread-specific storage for the set of hardware pipelines, by executing multiple SIMD floating-point operations using the execution circuitry and the first routing circuitry. This may improve performance and reduce power consumption for matrix multiply and reduction operations, for example.
Pipelined Allocation For Operand Cache
View pageUS Patent:
20200065104, Feb 27, 2020
Filed:
Aug 24, 2018
Appl. No.:
16/112614
Inventors:
- Cupertino CA, US
Terence M. Potter - Austin TX, US
Andrew M. Havlir - Orlando FL, US
Sivayya V. Ayinala - Austin TX, US
Terence M. Potter - Austin TX, US
Andrew M. Havlir - Orlando FL, US
Sivayya V. Ayinala - Austin TX, US
International Classification:
G06F 9/38
G06F 9/30
G06F 9/30
Abstract:
Techniques are disclosed relating to controlling an operand cache in a pipelined fashion. An operand cache may cache operands fetched from the register file or generated by previous instructions to improve performance and/or reduce power consumption. In some embodiments, instructions are pipelined and separate tag information is maintained to indicate allocation of an operand cache entry and ownership of the operand cache entry. In some embodiments, this may allow an operand to remain in the operand cache (and potentially be retrieved or modified) during an interval between allocation of the entry for another operand and ownership of the entry by the other operand. This may improve operand cache efficiency by allowing the entry to be used while to retrieving the other operand from the register file, for example.