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Sivayya Ayinala Phones & Addresses

  • Austin, TX
  • 3425 Grand Mesa Dr, Plano, TX 75025 (972) 943-0777
  • 3801 Spring Creek Pkwy, Plano, TX 75023 (972) 943-0777
  • Beaverton, OR
  • 106 Whitley Dr, Austin, TX 78738

Work

Position: Executive, Administrative, and Managerial

Education

Degree: High school graduate or higher

Publications

Us Patents

Multi-Threaded Dma

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US Patent:
7761617, Jul 20, 2010
Filed:
Mar 17, 2005
Appl. No.:
11/082564
Inventors:
Franck Seigneret - Roquefort les pins,
Sivayya Ayinala - Plano TX,
Nabil Khalifa - Saint Laurent du Van,
Praveen Kolli - Dallas TX,
Prabha Atluri - Plano TX,
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
G06F 13/00
US Classification:
710 22, 710 23, 710 24, 710 35
Abstract:
A direct memory access (DMA) circuit () includes a read port () and a write port (). The DMA circuit () is a multithreaded initiator with “m” threads on the read port () and “n” threads on the write port (). The DMA circuit () includes two decoupled read and write contexts and schedulers () that provide for more efficient buffering and pipelining. The schedulers () are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Multi-Channel Dma With Shared Fifo

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US Patent:
7373437, May 13, 2008
Filed:
Mar 15, 2005
Appl. No.:
11/080277
Inventors:
Franck Seigneret - Roquefort les pins,
Nabil Khalifa - Saint Laurent du Var,
Sivayya Ayinala - Plano TX,
Praveen Kolli - Dallas TX,
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
US Classification:
710 22, 710 26, 710308, 709212
Abstract:
A direct memory access (DMA) circuit () includes a read port () and a write port (). The DMA circuit () is a multithreaded initiator with “m” threads on the read port () and “n” threads on the write port (). The DMA circuit () includes a data FIFO () which is shared by all of the logical channels and the FIFO depth can be allocated dynamically allowing for the maximum number of channels to be scheduled and concurrently active. The FIFO () can also be allocated to a single channel if there is only one logical channel active. The FIFO () increases the DMA's transfer performance, pre-fetch capacity and buffering, while maximizing pipelining.

Apparatus And Method For Automatically Saving And Restoring Pad Configuration Registers Implemented In A Core Power Domain

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US Patent:
8117428, Feb 14, 2012
Filed:
Jun 4, 2009
Appl. No.:
12/478715
Inventors:
Alain Breton - Saint Paul,
Christophe Vatinel - Mouans Sartoux,
Sivayya Venkata Ayinala - Plano TX,
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 9/24
G06F 15/177
US Classification:
713 1, 713 2, 713320, 713323, 711100
Abstract:
According to various illustrative embodiments, an apparatus, system, and method for automatically saving and restoring pad configuration registers implemented in a core power domain are described. In one aspect, the apparatus comprises a save and restore logic component implemented in the core power domain and coupled to the pad configuration registers. The apparatus also comprises a memory instantiated in an always-on power domain and coupled to the save and restore logic component, the save and restore logic component implemented in the core power domain to automatically save the pad configuration registers in the memory in a pad configuration save process before a power supply to the core power domain is switched off and to automatically restore the pad configuration registers from the memory in a pad configuration restore process after the power supply to the core power domain is switched on.

Method And System For Reducing Power Consumption Of A Direct Memory Access Controller

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US Patent:
2006017, Aug 10, 2006
Filed:
Jan 28, 2005
Appl. No.:
11/045215
Inventors:
Sivayya Ayinala - Plano TX,
Praveen Kolli - Dallas TX,
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/28
US Classification:
710022000
Abstract:
A method and system for reducing the power consumption of a direct memory access (DMA) controller. A preferred method, for example, comprises: queuing a first DMA request in a queue; responding to the first queued DMA request when the computer system resources necessary for a DMA transfer are available; and placing at least some components of the computer system into a reduced power consumption state when the computer system resources necessary for the DMA transfer are not available.
Sivayya V Ayinala from Austin, TX, age ~52 Get Report