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Siddhartha C Chhabra

from Portland, OR
Age ~43
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Related to:
Kaur C Sukhmeet
Connected to:
Dhruv Chhabra, 30Harvind L Chhabra, 58Indu K Chhabra, 63Kuldeep S Chhabra, 59Kushal Chhabra, 52Mamta Chhabra, 48Manpreet Chhabra, 44Mayur R Chhabra, 44Meenu Chhabra, 52Meeta K Chhabra, 50

Siddhartha Chhabra Phones & Addresses

  • 5584 NW 131St Ave, Portland, OR 97229
  • Beaverton, OR
  • Raleigh, NC
  • 16593 NW Rossetta St, Portland, OR 97229

Resumes

Resumes

Siddhartha Chhabra Photo 1

Owner

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Location:
San Francisco, CA
Industry:
Furniture
Work:
Living Concept
Owner
Education:
Symbiosis Institute of Business Management, Pune 2013 - 2015
Master of Business Administration, Masters, International Business Rainbow School 1994 - 2008
Skills:
Asp.net
C++ Language
Xml
Jquery
Electronics
Networking
Matlab
Teamwork
Vhdl
Photoshop
Algorithms
Computer Science
Jsp
Research
English
Visual Basic
Languages:
English
Hindi
Punjabi
Certifications:
Import Export Licence & Certification (Dgft-Iec)
Siddhartha Chhabra Photo 2

Principal Engineer

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Location:
Hillsboro, OR
Work:
Intel Corporation
Principal Engineer
Siddhartha Chhabra Photo 3

Siddhartha Chhabra

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Publications

Us Patents

Low-Overhead Cryptographic Method And Apparatus For Providing Memory Confidentiality, Integrity And Replay Protection

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US Patent:
20140040632, Feb 6, 2014
Filed:
Dec 28, 2011
Appl. No.:
13/976930
Inventors:
Siddhartha Chhabra - Hillsboro OR, US
Uday R. Savagaonkar - Portlamd OR, US
Carlos V. Rozas - Portland OR, US
Alpa T. Narendra Trivedi - Hillsboro OR, US
Men Long - Beaverton OR, US
David M. Durham - Beaverton OR, US
International Classification:
G06F 21/64
US Classification:
713189
Abstract:
A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical read-after-write dependency between the various levels of the cryptographic tree. In one embodiment of the invention, the cryptographic processing of a child node can be pipelined with that of the parent nodes. This parallelization provided by the invention results in an efficient utilization of the cryptographic pipeline, enabling significantly lower performance overheads.

Circuitry And Methods For Supporting Encrypted Remote Direct Memory Access (Erdma) For Live Migration Of A Virtual Machine

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US Patent:
20220413886, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359117
Inventors:
- Santa Clara CA, US
DAVID BRONLEEWE - Hillsboro OR, US
HORMUZD KHOSRAVI - Portland OR, US
SIDDHARTHA CHHABRA - Portland OR, US
International Classification:
G06F 9/455
G06F 21/60
G06F 15/173
Abstract:
Systems, methods, and apparatuses to support encrypted remote direct memory access for live migration of a virtual machine are described. In one embodiment, a first computer system includes an encryption circuit in a hardware processor of the first computer system to encrypt data, a memory controller circuit, of the first computer system, comprising a port to couple to a network interface controller circuit, a direct memory access engine circuit of the first computer system to access a memory in the first computer system, and the hardware processor to, for a request to perform a live migration of a virtual machine from the first computer system to a second computer system via the network interface controller circuit: encrypt code and data of the virtual machine from the memory with an encryption key by the encryption circuit of the hardware processor, store the encrypted code and data of the virtual machine within a migration buffer of the memory of the first computer system by the direct memory access engine circuit, and cause the network interface controller circuit to send the encrypted code and data of the virtual machine from the migration buffer to the second computer system via the network interface controller circuit without the network interface controller circuit performing an additional encryption.

Handling Unaligned Transactions For Inline Encryption

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US Patent:
20220416997, Dec 29, 2022
Filed:
Jun 24, 2021
Appl. No.:
17/357973
Inventors:
- Santa Clara CA, US
Siddhartha Chhabra - Portland OR, US
Michael Glik - Kfar Saba M, IL
Baiju Patel - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/06
G06F 21/72
Abstract:
Methods and apparatus relating to handling unaligned transactions for inline encryption are described. In an embodiment, cryptographic logic circuitry receives a plurality of incoming packets and store two or more incoming packets from the plurality of incoming packets in memory. The cryptographic logic circuitry is informs software in response to detection of the two or more incoming packets. Other embodiments are also disclosed and claimed.

Methods And Apparatuses To Provide Chiplet Binding To A System On A Chip Platform Having A Disaggregated Architecture

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US Patent:
20220417005, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/358952
Inventors:
- Santa Clara CA, US
SIDDHARTHA CHHABRA - Portland OR, US
PRASHANT DEWAN - Portland OR, US
OFIR SHWARTZ - Haifa, IL
International Classification:
H04L 9/08
Abstract:
Systems, methods, and apparatuses for providing chiplet binding to a disaggregated architecture for a system on a chip are described. In one embodiment, system includes a plurality of physically separate dies, an interconnect to electrically couple the plurality of physically separate dies together, a first die-to-die communication circuit, of a first die of the plurality of physically separate dies, comprising a transmitter circuit and an encryption circuit having a link key to encrypt data to be sent from the transmitter circuit into encrypted data, and a second die-to-die communication circuit, of a second die of the plurality of physically separate dies, comprising a receiver circuit and a decryption circuit having the link key to decrypt the encrypted data sent from the transmitter circuit to the receiver circuit.

Technologies For Trusted I/O Protection Of I/O Data With Header Information

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US Patent:
20220405403, Dec 22, 2022
Filed:
Aug 18, 2022
Appl. No.:
17/820628
Inventors:
- Santa Clara CA, US
Siddhartha Chhabra - Portland OR, US
Bin Xing - Hillsboro OR, US
Pradeep M. Pappachan - Tualatin OR, US
Reshma Lal - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 21/60
H04L 9/40
G06F 21/57
G06F 13/28
H04L 9/32
G06F 21/62
G06F 21/85
G09C 1/00
G06F 13/20
Abstract:
Technologies for trusted I/O include a computing device having a hardware cryptographic agent, a cryptographic engine, and an I/O controller. The hardware cryptographic agent intercepts a message from the I/O controller and identifies boundaries of the message. The message may include multiple DMA transactions, and the start of message is the start of the first DMA transaction. The cryptographic engine encrypts the message and stores the encrypted data in a memory buffer. The cryptographic engine may skip and not encrypt header data starting at the start of message or may read a value from the header to determine the skip length. In some embodiments, the cryptographic agent and the cryptographic engine may be an inline cryptographic engine. In some embodiments, the cryptographic agent may be a channel identifier filter, and the cryptographic engine may be processor-based. Other embodiments are described and claimed.

Device Memory Protection For Supporting Trust Domains

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US Patent:
20220222185, Jul 14, 2022
Filed:
Apr 2, 2022
Appl. No.:
17/712109
Inventors:
- Santa Clara CA, US
Siddhartha Chhabra - Portland OR, US
David Puffer - Tempe AZ, US
Ankur Shah - Folsom CA, US
Daniel Nemiroff - El Dorado Hills CA, US
Utkarsh Y. Kakaiya - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/14
G06F 12/02
G06F 11/10
Abstract:
Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

Encryption Interface

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US Patent:
20220224510, Jul 14, 2022
Filed:
Mar 28, 2022
Appl. No.:
17/706288
Inventors:
- Santa Clara CA, US
Uday Savagaonkar - Portland OR, US
Alpa T. Narendra Trivedi - Hillsboro OR, US
Siddhartha Chhabra - Hillsboro OR, US
Baiju V. Patel - Portland OR, US
Men Long - Beaverton OR, US
Kirk S. Yap - Westborough MA, US
David M. Durham - Beaverton OR, US
International Classification:
H04L 9/06
G06F 12/14
G09C 1/00
G06F 21/85
G06F 21/60
Abstract:
Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.

Method And Apparatus For Run-Time Memory Isolation Across Different Execution Realms

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US Patent:
20220206951, Jun 30, 2022
Filed:
Dec 24, 2020
Appl. No.:
17/134052
Inventors:
- Santa Clara CA, US
Ramya JAYARAM MASTI - Hillsboro OR, US
Barry E. HUNTLEY - Hillsboro OR, US
Vincent VON BOKERN - Rescue CA, US
Siddhartha CHHABRA - Portland OR, US
Hormuzd M. KHOSRAVI - Portland OR, US
Vedvyas SHANBHOGUE - Austin TX, US
Gideon GERZON - Zichron Yaakov, IL
International Classification:
G06F 12/0895
G06F 12/06
G06F 9/455
G06F 21/53
G06F 12/14
Abstract:
A method is described. The method includes executing a memory access instruction for a software process or thread. The method includes creating a memory access request for the memory access instruction having a physical memory address and a first identifier of a realm that the software process or thread execute from. The method includes receiving the memory access request and determining a second identifier of a realm from the physical memory address. The method also includes servicing the memory access request because the first identifier matches the second identifier.
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Siddhartha C Chhabra from Portland, OR, age ~43 Get Report