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Shyam Pal

from Woodbridge, VA
Age ~61
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Connected to:
Adarsh Pal, 77Alex M Pal, 96Alexandra Pal, 29Alok K Pal, 52Anand Pal, 67Anjona Pal, 50Ashish D Pal, 58Ashwin A Pal, 44Aswini Pal, 49Avinash Pal, 44

Shyam Pal Phones & Addresses

  • Woodbridge, VA
  • Saratoga Springs, UT
  • Clifton Park, NY
  • Ballston Spa, NY
  • Beacon, NY

Work

Company: Jindal steel and power ltd raigarh Nov 2005 Position: Dy manager

Education

School / High School: College, Raipur and BHU- india 2003 Specialities: B.E., Mtech in metallurgy

Skills

EAF operation • efficient and careful

Resumes

Resumes

Shyam Pal Photo 1

Shyam Pal

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Shyam Pal Photo 2

Shyam Pal 492013, IN

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Work:
Jindal Steel and Power Ltd Raigarh

Nov 2005 to 2000
Dy Manager
National Metallurgical Laboratory (C.S.I.R

Sep 2004 to Jun 2005
Bhilai Steel Plant

May 2002 to Jun 2002
Education:
College, Raipur and BHU
india
2003
B.E., Mtech in metallurgy
Skills:
EAF operation, efficient and careful
Shyam Pal Photo 3

Shyam Pal

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Publications

Us Patents

Siloxane And Organic-Based Mol Contact Patterning

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US Patent:
20170200792, Jul 13, 2017
Filed:
Jan 12, 2016
Appl. No.:
14/993537
Inventors:
- Grand Cayman, KY
Andy WEI - Dresden, DE
Anthony OZZELLO - Austin TX, US
Bharat KRISHNAN - Clifton Park NY, US
Guillaume BOUCHE - Albany NY, US
Haifeng SHENG - Rexford NY, US
Huang LIU - Mechanicville NY, US
Huy M. CAO - Rexford NY, US
Ja-Hyung HAN - Clifton Park NY, US
SangWoo LIM - Ballston Spa NY, US
Kenneth A. BATES - Happy Valley OR, US
Shyam PAL - Clifton Park NY, US
Xintuo DAI - Rexford NY, US
Jinping LIU - Ballston Lake NY, US
International Classification:
H01L 29/40
H01L 21/02
H01L 21/28
H01L 29/423
Abstract:
Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Method For Fabricating A Semiconductor Integrated Circuit With A Litho-Etch, Litho-Etch Process For Etching Trenches

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US Patent:
20140235055, Aug 21, 2014
Filed:
Feb 15, 2013
Appl. No.:
13/767993
Inventors:
- Grand Cayman, KY
Norman Chen - Poughkeepsie NY, US
Yuyang Sun - Wappingers Falls NY, US
Matthew Herrick - Mechanicville NY, US
Shyam Pal - Clifton Park NY, US
Jeong Soo Kim - Clifton Park NY, US
Assignee:
GLOBALFOUNDRIES, INC. - Grand Cayman
International Classification:
H01L 21/308
US Classification:
438694
Abstract:
Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.
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Shyam Pal from Woodbridge, VA, age ~61 Get Report