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Shu Q Qin

from Hopkinton, MA
Age ~74
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Also known as:
Zhen Qin, Shu Win
Related to:
Monica A Tyree, 54Sheila A Anderson, 89
Connected to:
Bin Y Qin, 60Chin F Qin, 69Christine H Qin, 56Cong C Qin, 53Da G Qin, 67Dennis B Qin, 38Fen H Qin, 61Guo H Qin, 41Henry Qin, 35Huiqing Qin, 53

Shu Qin Phones & Addresses

  • Hopkinton, MA
  • 55 Forest Ave, Everett, MA 02149
  • 47 Francis St APT 2, Malden, MA 02148 (781) 864-7246
  • 47 Francis St, Malden, MA 02148
  • 26 Clarendon St, Malden, MA 02148
  • 4141 W Nez Perce St APT 117, Boise, ID 83705
  • 1001 Leadville Ave, Boise, ID 83706
  • Boston, MA
  • Auburndale, MA

Publications

Us Patents

Mems Based Contact Conductivity Electrostatic Chuck

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US Patent:
6905984, Jun 14, 2005
Filed:
Oct 10, 2003
Appl. No.:
10/683679
Inventors:
Peter L. Kellerman - Essex MA, US
Shu Qin - Malden MA, US
Ernie Allen - Rockport MA, US
Douglas A. Brown - S. Hamilton MA, US
Assignee:
Axcelis Technologies, Inc. - Beverly MA
International Classification:
H01L021/00
US Classification:
438964, 438597
Abstract:
The present invention is directed to a method for clamping and processing a semiconductor substrate using a semiconductor processing apparatus. According to one aspect of the present invention, a multi-polar electrostatic chuck and associated method is disclosed which provides heating or cooling of a substrate by thermal contact conduction between the electrostatic chuck and the substrate. The multi-polar electrostatic chuck includes a semiconductor platform having a plurality of protrusions that define gaps therebetween, wherein a surface roughness of the plurality of protrusions is less than 100 Angstroms. The electrostatic chuck further includes a voltage control system operable to control a voltage applied to the electrostatic chuck to thus control a contact heat transfer coefficient of the electrostatic chuck, wherein the heat transfer coefficient of the electrostatic chuck is primarily a function of a contact pressure between the substrate and the plurality of protrusions.

Method Of Making A Mems Electrostatic Chuck

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US Patent:
6946403, Sep 20, 2005
Filed:
Oct 28, 2003
Appl. No.:
10/695153
Inventors:
Peter L. Kellerman - Essex MA, US
Shu Qin - Malden MA, US
Ernie Allen - Rockport MA, US
Douglas A. Brown - S. Hamilton MA, US
Assignee:
Axcelis Technologies, Inc. - Beverly MA
International Classification:
H01L021/469
US Classification:
438758, 438761, 438778, 438800
Abstract:
The present invention is directed to a method of forming a clamping plate for a multi-polar electrostatic chuck. The method comprises forming a first electrically conductive layer over a semiconductor platform and defining a plurality of portions of the first electrically conductive layer which are electrically isolated from one another. A first electrically insulative layer is formed over the first electrically conductive layer, the first electrically insulative layer comprising a top surface having a plurality of MEMS protrusions extending a first distance therefrom. A plurality of poles are furthermore electrically connected to the respective plurality of portions of the first electrically conductive layer, wherein a voltage applied between the plurality of poles is operable to induce an electrostatic force in the clamping plate.

Clamping And De-Clamping Semiconductor Wafers On An Electrostatic Chuck Using Wafer Inertial Confinement By Applying A Single-Phase Square Wave Ac Clamping Voltage

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US Patent:
6947274, Sep 20, 2005
Filed:
Sep 8, 2003
Appl. No.:
10/657449
Inventors:
Peter L. Kellerman - Essex MA, US
Shu Qin - Malden MA, US
William F. DiVergilio - Beverly MA, US
Assignee:
Axcelis Technologies, Inc. - Beverly MA
International Classification:
H01F013/02
US Classification:
361234, 361235
Abstract:
The present invention is directed to a method for clamping a wafer to an electrostatic chuck using a single-phase square wave AC clamping voltage. The method comprises determining a single-phase square wave clamping voltage for the electrostatic chuck, wherein the determination is based, at least in part, on an inertial response time of the wafer. The wafer is placed on the electrostatic chuck, wherein a gap between the electrostatic chuck and the wafer is defined. The determined single-phase square wave clamping voltage is then applied, wherein the wafer is generally clamped to the electrostatic chuck within a predetermined distance, while an amount of electrostatic charge is generally not allowed to accumulate, thereby enabling a fast de-clamping of the wafer.

Mems Based Multi-Polar Electrostatic Chuck

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US Patent:
7072165, Jul 4, 2006
Filed:
Aug 18, 2003
Appl. No.:
10/642939
Inventors:
Peter L. Kellerman - Essex MA, US
Shu Qin - Malden MA, US
Douglas A. Brown - S. Hamilton MA, US
Assignee:
Axcelis Technologies, Inc. - Beverly MA
International Classification:
H01L 21/683
US Classification:
361234, 361233
Abstract:
The present invention is directed to a semiconductor processing apparatus and a method for clamping a semiconductor substrate and controlling a heat transfer associated therewith. According to one aspect of the present invention, a multi-polar electrostatic chuck and associated method is disclosed which provides a controlled and uniform heat transfer coefficient across a surface thereof. The multi-polar electrostatic chuck comprises a semiconductor platform having a plurality of protrusions that define gaps therebetween, wherein a distance or depth of the gaps is uniform and associated with a mean free path of the cooling gas therein. The electrostatic chuck is permits a control of a backside pressure of a cooling gas within the plurality of gaps to thus control a heat transfer coefficient of the cooling gas. The plurality of protrusions further provide a uniform contact surface, wherein a contact conductivity between the plurality of protrusions and the substrate is controllable and significantly uniform across the substrate.

Clamping And De-Clamping Semiconductor Wafers On A J-R Electrostatic Chuck Having A Micromachined Surface By Using Force Delay In Applying A Single-Phase Square Wave Ac Clamping Voltage

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US Patent:
7072166, Jul 4, 2006
Filed:
Sep 12, 2003
Appl. No.:
10/661180
Inventors:
Shu Qin - Malden MA, US
Peter L. Kellerman - Essex MA, US
Assignee:
Axcelis Technologies, Inc. - Beverly MA
International Classification:
H01H 1/00
US Classification:
361234
Abstract:
The present invention is directed to a method and a system for clamping a wafer to a J-R electrostatic chuck using a single-phase square wave AC clamping voltage. The method comprises determining a single-phase square wave clamping voltage for the J-R electrostatic chuck, wherein the determination is based, at least in part, on a minimum residual clamping force associated with the wafer and the electrostatic chuck and a surface topography of a leaky dielectric layer associated therewith. The wafer is placed on the electrostatic chuck; and the determined clamping voltage is applied to the electrostatic chuck, therein electrostatically clamping the wafer to the electrostatic chuck, wherein at least the minimum residual clamping force is maintained during a polarity switch of the single-phase square wave clamping voltage. The determination of the surface topography comprises a first gap and a second gap between the wafer and the electrostatic chuck and an island area ratio, wherein a difference in RC time constants associated with the respective first gap and second gap is provided such that at least the minimum residual clamping force is maintained during the polarity switch. Upon removal of the square wave clamping voltage, the de-clamping time is substantially reduced, and corresponds to the pulse width of the square wave clamping voltage.

Low-K Dielectric Process For Multilevel Interconnection Using Mircocavity Engineering During Electric Circuit Manufacture

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US Patent:
7235493, Jun 26, 2007
Filed:
Oct 18, 2004
Appl. No.:
10/968786
Inventors:
Shu Qin - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/311
US Classification:
438739, 438619, 438622, 257637
Abstract:
One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form a plurality of hemispherical microcavities in the silicon dioxide. Openings in the patterned nitride are filled, then another layer is formed over the silicon nitride layer using the silicon nitride as a support over the microcavities. An inventive structure resulting from the method is also described.

Systems And Methods For Plasma Processing Of Microfeature Workpieces

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US Patent:
7476556, Jan 13, 2009
Filed:
Aug 11, 2005
Appl. No.:
11/201668
Inventors:
Shu Qin - Boise ID, US
Allen McTeer - Eagle ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/66
H01L 21/00
US Classification:
438 16, 438 8, 438 9, 438 14, 257E21218, 257E21143
Abstract:
Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.

Methods For Determining A Dose Of An Impurity Implanted In A Semiconductor Substrate

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US Patent:
7592212, Sep 22, 2009
Filed:
Apr 6, 2007
Appl. No.:
11/784241
Inventors:
Shu Qin - Boise ID, US
Allen McTeer - Eagle ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/337
US Classification:
438181
Abstract:
Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a plasma generated by the plasma doping process and a ratio of each impurity-based ion species to a total impurity-based ion species in the plasma are directly measured. The ratios may be directly measured by ion mass spectroscopy. The total ion dose and the ratios are used to determine the total impurity dose. The apparatus includes an ion detector, an ion mass spectrometer, a dosimeter, and software.
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Shu Q Qin from Hopkinton, MA, age ~74 Get Report