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Shin-Nan Sun

from Fremont, CA
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Related to:
Eric SunShinnan Sun, 56Richard Sun, 30Ivana Huang, 61Chen L Lin, 67Yichen Lin, 56
Connected to:
Abby Sun, 31Andy H Sun, 45Argus M Sun, 46Asa Sun, 39Audrey A Sun, 62Bili A Sun, 27Bill Sun, 60Bingxin Sun, 39Bo Sun, 41Boqin Sun, 40

Shin-Nan Sun Phones & Addresses

  • 1530 Salamanca Ct, Fremont, CA 94539 (510) 668-1030

Publications

Us Patents

Clock-Generator Architecture For A Programmable-Logic-Based System On A Chip

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US Patent:
7102391, Sep 5, 2006
Filed:
Jul 29, 2004
Appl. No.:
10/903473
Inventors:
Shin-Nan Sun - Fremont CA, US
Limin Zhu - Fremont CA, US
Theodore Speers - San Jose CA, US
Gregory Bakker - San Jose CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
H03D 9/00
US Classification:
327 10, 327 99, 327298
Abstract:
A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Parallel Programmable Antifuse Field Programmable Gate Array Device (Fpga) And A Method For Programming And Testing An Antifuse Fpga

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US Patent:
7111272, Sep 19, 2006
Filed:
Apr 27, 2004
Appl. No.:
10/833608
Inventors:
Shin-Nan Sun - Fremont CA, US
Wayne W. Wong - Sunnyvale CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
H03K 17/693
H03K 19/173
G06F 17/50
US Classification:
716 16, 716 17, 326 47
Abstract:
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

Clock-Generator Architecture For A Programmable-Logic-Based System On A Chip

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US Patent:
7298178, Nov 20, 2007
Filed:
Jun 29, 2006
Appl. No.:
11/427717
Inventors:
Shin-Nan Sun - Fremont CA, US
Limin Zhu - Fremont CA, US
Theodore Speers - San Jose CA, US
Gregory Bakker - San Jose CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
H03D 9/00
US Classification:
327 10, 327 99, 327298
Abstract:
A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Clock-Generator Architecture For A Programmable-Logic-Based System On A Chip

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US Patent:
7501872, Mar 10, 2009
Filed:
Oct 12, 2007
Appl. No.:
11/871741
Inventors:
Shin-Nan Sun - Fremont CA, US
Limin Zhu - Fremont CA, US
Theodore Speers - San Jose CA, US
Gregory Bakker - San Jose CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
H03K 3/00
US Classification:
327298, 327 99, 327294
Abstract:
A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Parallel Programmable Antifuse Field Programmable Gate Array Device (Fpga) And A Method For Programming And Testing An Antifuse Fpga

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US Patent:
7549138, Jun 16, 2009
Filed:
Aug 13, 2007
Appl. No.:
11/837700
Inventors:
Shin-Nan Sun - Fremont CA, US
Wayne W. Wong - Sunnyvale CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
G06F 17/50
G06F 7/38
H03K 19/173
US Classification:
716 16, 326 37
Abstract:
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

Clock-Generator Architecture For A Programmable-Logic-Based System On A Chip

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US Patent:
7579895, Aug 25, 2009
Filed:
Oct 31, 2007
Appl. No.:
11/932807
Inventors:
Shin-Nan Sun - Fremont CA, US
Limin Zhu - Fremont CA, US
Theodore Speers - San Jose CA, US
Gregory Bakker - San Jose CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
H03K 17/62
US Classification:
327407, 327 99, 327298
Abstract:
A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Parallel Programmable Antifuse Field Programmable Gate Array Device (Fpga) And A Method For Programming And Testing An Antifuse Fpga

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US Patent:
7269814, Sep 11, 2007
Filed:
Sep 18, 2006
Appl. No.:
11/532757
Inventors:
Shin-Nan Sun - Fremont CA, US
Wayne W. Wong - Sunnyvale CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
G06F 17/50
G06F 7/38
H01L 25/00
H03K 17/693
US Classification:
716 16, 716 17, 326 37, 326 41
Abstract:
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

Parallel Programmable Antifuse Field Programmable Gate Array Device (Fpga) And A Method For Programming And Testing An Antifuse Fpga

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US Patent:
6885218, Apr 26, 2005
Filed:
Oct 8, 2002
Appl. No.:
10/267917
Inventors:
Shin-Nan Sun - Fremont CA, US
Wayne W. Wong - Sunnyvale CA, US
Assignee:
Actel Corporation - Mountain View CA
International Classification:
H03K019/177
US Classification:
326 41, 326 47
Abstract:
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.
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Shin-Nan Sun from Fremont, CA Get Report