Shesh Mani Pandey

20210313321, Oct 7, 2021

Apr 7, 2020

16/842075

- Santa Clara CA, US
Sipeng Gu - Clifton Park NY, US
Shesh Mani Pandey - Saratoga Springs NY, US
Lixia Lei - Clifton Park NY, US
Gregory Costrini - Flanders NJ, US

H01L 27/088
H01L 29/06
H01L 29/78
H01L 27/092
H01L 21/8234

One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

20210151451, May 20, 2021

Nov 14, 2019

16/683439

- Santa Clara CA, US
Ruilong Xie - Niskayuna NY, US
Shesh Mani Pandey - Saratoga Springs NY, US

H01L 27/11556
H01L 27/11582
H01L 29/51
H01L 29/423

One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

20210043766, Feb 11, 2021

Aug 7, 2019

16/533835

- Grand Cayman, KY
Shesh Mani Pandey - Saratoga Springs NY, US
Jiehui Shu - Clifton Park NY, US
Sipeng Gu - Clifton Park NY, US
Haiting Wang - Clifton Park NY, US

H01L 29/78
H01L 29/66

A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.

20200388707, Dec 10, 2020

Jun 6, 2019

16/434136

- Grand Cayman, KY
XIAOXIAO ZHANG - Clifton Park NY, US
SHESH MANI PANDEY - Saratoga Springs NY, US
HUI ZANG - Guilderland NY, US

H01L 29/78
H01L 29/51
H01L 29/10
H01L 29/49
H01L 21/28
H01L 29/66
H01L 21/311

The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component. The present disclosure provides a semiconductor device having first and second gate structures disposed in a dielectric layer above an active region, the first gate structure has a first width that is smaller than a second width of the second gate structure, a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface, and a first gate electrode disposed in the first WFM layer and a second gate electrode having a lower portion disposed in the second WFM layer, where the first gate electrode has a first width that is smaller than a second width of the second gate electrode.

20200335594, Oct 22, 2020

Apr 17, 2019

16/386545

- Grand Cayman, KY
Shesh Mani Pandey - Saratoga Springs NY, US

H01L 29/423
H01L 21/28
H01L 21/8234
H01L 29/78
H01L 29/06
H01L 21/768
H01L 21/321

Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

20200227404, Jul 16, 2020

Jan 10, 2019

16/244169

- Grand Cayman, KY
Guowei Xu - Ballston Lake NY, US
Jiehui Shu - Clifton Park NY, US
Ruilong Xie - Niskayuna NY, US
Yurong Wen - Singapore, SG
Garo J. Derderian - Saratoga Springs NY, US
Shesh M. Pandey - Saratoga Springs NY, US
Laertis Economikos - Wappingers Falls NY, US

H01L 27/06
H01L 49/02
H01L 21/762
H01L 29/78
H01L 29/40
H01L 29/66
H01L 23/522

An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

20200111713, Apr 9, 2020

Oct 3, 2018

16/150651

- GRAND CAYMAN, KY
Laertis Economikos - Wappingers Falls NY, US
Shesh Mani Pandey - Saratoga Springs NY, US
Chanro Park - Clifton Park NY, US
Ruilong Xie - Schenectady NY, US

GLOBALFOUNDRIES INC. - GRAND CAYMAN

H01L 21/8234
H01L 27/088
H01L 21/762
H01L 29/417
H01L 29/66
H01L 29/78

Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

20200091005, Mar 19, 2020

Sep 18, 2018

16/134708

- Grand Cayman, KY
Balaji Kannan - Clifton Park NY, US
Shesh Mani Pandey - Saratoga Springs NY, US
Haiting Wang - Clifton Park NY, US

H01L 21/8234
H01L 27/088
H01L 29/66

A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.