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Sheng-Hsiung H Hsueh

from San Jose, CA
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Related to:
Juyu W Hsueh, 65Jessica Hsueh, 34Jennifer Hsueh, 31Janet Hsueh, 32Angela Grant, 57Sheng H Hsueh, 67
Connected to:
Eric C Hsueh, 45Fang H Hsueh, 64Franklin C Hsueh, 70Jay Hsueh, 41Judy C Hsueh, 70Julie Y Hsueh, 73Kelly Hsueh, 40Lee C Hsueh, 72Martha T Hsueh, 60Sharon Hsueh, 29

Sheng-Hsiung Hsueh Phones & Addresses

  • 6610 Graystone Meadow Cir, San Jose, CA 95120 (408) 268-1267

Publications

Us Patents

Method For Handling A Defective Top Gate Of A Source-Side Injection Flash Memory Array

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US Patent:
7447073, Nov 4, 2008
Filed:
Feb 16, 2007
Appl. No.:
11/707341
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/34
US Classification:
36518515, 36518514, 36518509, 36518522, 36518518, 36518529
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array Having Control/Decode Circuitry For Disabling Top Gates Of Defective Memory Cells

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US Patent:
7567458, Jul 28, 2009
Filed:
Sep 26, 2005
Appl. No.:
11/235901
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/34
US Classification:
36518515, 36518514, 36518509, 36518511, 36518503, 36518523
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array System Including A Top Gate Memory Cell

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US Patent:
7626863, Dec 1, 2009
Filed:
Feb 16, 2007
Appl. No.:
11/707343
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/04
US Classification:
36518515, 36518514, 36518503
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array With A Top Gate Line Dynamically Coupled To A Word Line

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US Patent:
7663921, Feb 16, 2010
Filed:
Nov 7, 2008
Appl. No.:
12/267519
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/04
US Classification:
36518515, 36518514, 36518526, 36518503, 36518523, 36518519, 36518512, 36518511
Abstract:
Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.

Flash Memory Array System Including A Top Gate Memory Cell

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US Patent:
7778080, Aug 17, 2010
Filed:
Aug 28, 2008
Appl. No.:
12/200930
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/34
US Classification:
36518515, 36518514, 36518509, 36518522, 36518529
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array System Including A Top Gate Memory Cell

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US Patent:
7848140, Dec 7, 2010
Filed:
Jul 22, 2009
Appl. No.:
12/507783
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/04
US Classification:
36518502, 36518503, 36518515, 36518514, 36518511, 36518523, 36518526
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array System Including A Top Gate Memory Cell

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US Patent:
8270213, Sep 18, 2012
Filed:
Dec 7, 2010
Appl. No.:
12/962343
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - San Jose CA
International Classification:
G11C 16/12
US Classification:
36518502, 36518503, 36518515, 36518514, 36518511, 36518523, 36518526, 36518518
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Dual Reference Cell For Split-Gate Nonvolatile Semiconductor Memory

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US Patent:
6687162, Feb 3, 2004
Filed:
Apr 19, 2002
Appl. No.:
10/126450
Inventors:
Sheng-Hsiung Hsueh - San Jose CA
Ganshu Ben Lee - Santa Clara CA
Loc Bao Hoang - San Jose CA
Albert V. Kordesch - San Jose CA
Assignee:
Winbond Electronics Corporation - Hsin Chu
International Classification:
G11C 1606
US Classification:
36518521, 3651852
Abstract:
Techniques to more accurately read values stored in data cells. In an aspect, one reference cell is provided for each group of data cells having similar configuration (e. g. , similar layout and orientation). For split-gate memory cells arranged in pairs, each pair includes two data cells implemented as mirrored image of one another. Two reference cells may then be used, one reference cell for each data cell in a pair. In another aspect, the data paths for the reference and data cells for read operation are matched. This matching may be achieved by using the same circuit design for the data and reference sense amplifiers, using the same layout and orientation for the sense amplifiers, matching the lines for the two data paths, matching the structure (e. g. , length and width) and the diffusion region (e. g. , doping concentration and contact) for the sense amplifiers and lines, and so on.
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Sheng-Hsiung H Hsueh from San Jose, CA Get Report