Shaun K Ho

6417858, Jul 9, 2002

Dec 23, 1998

09/220156

Derek Bosch - Mountain View CA
Carroll Philip Gossett - Mountain View CA
Ian ODonnell - Berkeley CA
Anan Nagarajan - Palo Alto CA
Adrian Jeday - San Francisco CA
Eric Demers - Redwood City CA
Vimal Parikh - Fremont CA
Shaun Ho - Cupertino CA

Microsoft Corporation - Redmond WA

G06T 100

345522, 345503, 345426, 712245

A processor for computer graphics calculations comprising an entire graphics engine in a single integrated circuit. The processor includes a transform mechanism adapted to compute transforms for the computer graphics calculations. The transform mechanism includes a transformation element adapted to compute transforms using a dot product operation. The transform mechanism of the processor also includes a perspective division element, a color unit for lighting calculations, a scaling element for multiplication operations, and a look-up table containing mathematical functions used by the computer graphics calculations. The processor also includes a raster unit coupled to the transform mechanism, a texture unit coupled to the raster unit, and a shader unit coupled to the texture unit.

7075539, Jul 11, 2006

May 30, 2003

10/452658

Thomas H. Kong - Los Altos CA, US
Shaun Ho - Los Altos CA, US
Matthew Papakipos - Palo Alto CA, US

NVIDIA Corporation - Santa Clara CA

G06T 1/00
G06K 9/72
G06F 7/00

345501, 382235, 708203

A computing system has a graphics processor, a graphics memory, main memory, a bridge, and a central processing unit configured to process floating-point data of a first fixed size. An interconnect grid includes communication paths to link the graphics processor, the graphics memory, main memory, the bridge, and the central processing unit. A computing system component (e. g. , the graphics processor or central processing unit) converts floating-point data to graphics floating-point data with a fixed size smaller than the fixed size of the floating-point data. The computing system passes the floating-point data and/or the graphics floating-point data over at least a portion of the interconnect grid. Alternately, the graphics processor may directly read and process previously compressed and stored graphics floating-point data.

7081895, Jul 25, 2006

Apr 11, 2003

10/411940

Matthew N. Papakipos - Palo Alto CA, US
Rui M. Bastos - Santa Clara CA, US
Christian Rouet - San Francisco CA, US
Shaun Ho - Los Altos CA, US

NVIDIA Corporation - Santa Clara CA

G06T 1/20
G06F 15/16
G09G 5/00

345506, 345503, 345419, 345582

Method and apparatus for graphics processing is described. More particularly, a graphics processing subsystem capable of multi-pass graphics data processing is described. The graphics processing subsystem includes a geometry processor and a fragment processor, where output from the fragment processor is input compatible with the geometry processor. Data produced in a pass through a graphics data-processing pipeline including the fragment processor and geometry processor may be used as an input to processing during a subsequent pass. Data read from a texture map may be used to define or modify data, including vertex data, being processed in the geometry processor or the fragment processor.

7508394, Mar 24, 2009

Jul 10, 2006

11/484034

Matthew N. Papakipos - Palo Alto CA, US
Rui M. Bastos - Santa Clara CA, US
Christian Rouet - San Francisco CA, US
Shaun Ho - Los Altos CA, US

NVIDIA Corporation - Santa Clara CA

G06T 1/20

345506

Method and apparatus for graphics processing is described. More particularly, a graphics processing subsystem capable of multi-pass graphics data processing is described. The graphics processing subsystem includes a geometry processor and a fragment processor, where output from the fragment processor is input compatible with the geometry processor. Data produced in a pass through a graphics data-processing pipeline including the fragment processor and geometry processor may be used as an input to processing during a subsequent pass. Data read from a texture map may be used to define or modify data, including vertex data, being processed in the geometry processor or the fragment processor.

63337444, Dec 25, 2001

Mar 22, 1999

9/273975

David B. Kirk - San Francisco CA
Matthew Papakipos - Palo Alto CA
Shaun Ho - Cupertino CA
Walter Donovan - Milpitas CA
Curtis Priem - Fremont CA

Nvidia Corporation - Santa Clara CA

G06T 120

345506

A graphics pipeline including a rasterizing stage producing diffuse color values; a plurality of texture stages producing texture values defining a particular texture; a combiner stage for combining four of a plurality of selectable input values including diffuse color values, texture values furnished by a plurality of texture stages, and proportions for combination of the selectable input values; the combiner stage being capable of providing a result equivalent to a sum of products of any two sets of input values, and a product of two input values.

62978330, Oct 2, 2001

Mar 23, 1999

9/274985

Shaun Ho - Cupertino CA
Douglas H. Rogers - Sunnyvale CA
Paolo Sabella - Pleasanton CA

Nvidia Corporation - Santa Clara CA

G06T 1140

345581

A graphics accelerator pipeline including a rasterizer stage, a texture stage, and a combiner stage capable of producing realistic output images by mapping irregular textures to surfaces.