Resumes
Resumes
Sharad Sambhwani Phones & Addresses
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5254 Foxborough Pt, San Diego, CA 92130 (858) 344-2181
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6610 Hollycrest Ct, San Diego, CA 92121 (858) 202-1685
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Brooklyn, NY
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274 Marcia Way, Bridgewater, NJ 08807 (908) 707-9869
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San Francisco, CA
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Avenel, NJ
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Rochester, NY
Work
Position:
Executive, Administrative, and Managerial Occupations
Education
Degree:
High school graduate or higher
Emails
Publications
Us Patents
Low Power Long Code Synchronization Scheme For Sleep Mode Operation Of Cdma Systems
View pageUS Patent:
6788668, Sep 7, 2004
Filed:
Feb 29, 2000
Appl. No.:
09/515222
Inventors:
Yogendra Champaklal Shah - Morganville NJ
Karim Nassiri Toussi - San Jose CA
Sharad D. Sambhwani - Bridgewater NJ
Karim Nassiri Toussi - San Jose CA
Sharad D. Sambhwani - Bridgewater NJ
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04B 7216
US Classification:
370342, 370337, 370318, 370503, 370441, 455522, 455 134, 375130
Abstract:
In one embodiment, the present invention is a method for conserving power supplied to a linear feedback shift register (LFSR) long code (LC) generator, the method including steps of operating the LC generator during pre-assigned time slots; shutting off the LC generator during standby periods between the pre-assigned time slots; and priming starting states of the LC generator for synchronization with pre-assigned time slots following a standby period. This embodiment of the present invention enables power to be removed from the LFSR LC generator as well as the LFSR clock. Because the accuracy of the LFSR clock is usually derived from a system master transistor-controlled crystal oscillator (TCXO), and because the LFSR clock operates at a relatively high rate, the TCXO can also be powered down to conserve power. A low frequency, low power clock source can then be used instead of the higher powered clock source and TCXO to maintain operation of the mobile during the mobile sleep state.
Low I/O Bandwidth Method And System For Implementing Detection And Identification Of Scrambling Codes
View pageUS Patent:
7088825, Aug 8, 2006
Filed:
Dec 12, 2001
Appl. No.:
10/015531
Inventors:
Sharad Sambhwani - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Assignee:
Quicksilver Technology, Inc. - San Jose CA
International Classification:
H04N 7/167
US Classification:
380268, 380276
Abstract:
A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding segment of the master scrambling code. For every sixteen (16) chips, a new segment of the master scrambling code is introduced into one of the correlators, a segment of the master scrambling code is dropped from another correlator, and segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding segments of the master scrambling code and newly received signals.
Method And System For Detecting And Identifying Scrambling Codes
View pageUS Patent:
7139256, Nov 21, 2006
Filed:
Dec 12, 2001
Appl. No.:
10/015537
Inventors:
Sharad Sambhwani - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Assignee:
Quicksilver Technology, Inc. - Palo Alto CA
International Classification:
H04B 7/216
H04B 1/69
H04B 1/69
US Classification:
370335, 370342, 375137, 375142
Abstract:
A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals.
Low I/O Bandwidth Method And System For Implementing Detection And Identification Of Scrambling Codes
View pageUS Patent:
7197645, Mar 27, 2007
Filed:
Aug 3, 2006
Appl. No.:
11/498647
Inventors:
Sharad D. Sambhwani - San Diego CA, US
Ghobad Heidari-Bateni - San Diego CA, US
Ghobad Heidari-Bateni - San Diego CA, US
Assignee:
QST Holdings, LLC. - Palo Alto CA
International Classification:
G06F 9/24
US Classification:
713179, 713193, 713168
Abstract:
A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding segment of the master scrambling code. For every sixteen (16) chips, a new segment of the master scrambling code is introduced into one of the correlators, a segment of the master scrambling code is dropped from another correlator, and segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding segments of the master scrambling code and newly received signals.
Low I/O Bandwidth Method And System For Implementing Detection And Identification Of Scrambling Codes
View pageUS Patent:
7215701, May 8, 2007
Filed:
Nov 14, 2002
Appl. No.:
10/295692
Inventors:
Sharad Sambhwani - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Ghobad Heidari - San Diego CA, US
International Classification:
H04B 1/00
US Classification:
375150
Abstract:
A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code. For every sixteen (16) chips, a new X-component segment of the master scrambling code is introduced into one of the correlators, a X-component segment of the master scrambling code is dropped from another correlator, and X-component segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding X-component segments of the master scrambling code and newly received signals.
Viterbi Decoder With Survivor Bits Stored To Support Look-Ahead Addressing
View pageUS Patent:
7331013, Feb 12, 2008
Filed:
Feb 18, 2004
Appl. No.:
10/784484
Inventors:
John M. Rudosky - Portsmouth NH, US
Brian Box - Seabrook NH, US
Sharad Sambhwani - San Diego CA, US
Aixin Liu - San Diego CA, US
Brian Box - Seabrook NH, US
Sharad Sambhwani - San Diego CA, US
Aixin Liu - San Diego CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H03M 13/41
US Classification:
714795
Abstract:
In accordance with an embodiment of the present invention, a Viterbi decoder is described that operates on convolutional error correcting codes. The decoder allows for a pipelined architecture and a unique partitioning of survivor memory to maintain data integrity. Throughput rate is improved and stalling minimized by accessing memory words using a look-ahead function to fill the pipeline.
Data Flow Control For Adaptive Integrated Circuitry
View pageUS Patent:
7353516, Apr 1, 2008
Filed:
Aug 14, 2003
Appl. No.:
10/641976
Inventors:
Ghobad Heidari-Bateni - San Diego CA, US
Sharad D. Sambhwani - San Diego CA, US
Sharad D. Sambhwani - San Diego CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 9/46
G06F 9/40
G06F 9/44
G06F 9/40
G06F 9/44
US Classification:
718102, 712200, 712201, 712220, 712221
Abstract:
The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution based upon data consumption measured in data buffer units. In the various embodiments, when a first task of a plurality of tasks is initiated, buffer parameter is determined and a buffer count is initialized for the first task. For each iteration of the first task using a data buffer unit of input data, the buffer count is correspondingly adjusted, such as incremented or decremented. When the buffer count meets the buffer parameter requirements, the state of the first task is changed, which may including stopping the first task, and a next action is determined, such as initiating a second task. The various apparatus embodiments include a hardware task manager, a node sequencer, a programmable node, and use of a monitoring task within an adaptive execution unit.
Low I/O Bandwidth Method And System For Implementing Detection And Identification Of Scrambling Codes
View pageUS Patent:
7512173, Mar 31, 2009
Filed:
Mar 13, 2007
Appl. No.:
11/724076
Inventors:
Sharad Sambhwani - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Ghobad Heidari - San Diego CA, US
Assignee:
QST Holdings, LLC - Palo Alto CA
International Classification:
H04B 1/00
US Classification:
375150
Abstract:
A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code. For every sixteen (16) chips, a new X-component segment of the master scrambling code is introduced into one of the correlators, a X-component segment of the master scrambling code is dropped from another correlator, and X-component segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding X-component segments of the master scrambling code and newly received signals.