Shantanu K Sarangi

20220365857, Nov 17, 2022

May 13, 2021

17/320025

- Santa Clara CA, US
Anitha Kalva - San Jose CA, US
Abilash Nerallapally - San Jose CA, US
Milind Sonawane - Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US
Ashok Aravamudhan - Beaverton OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Sam Edirisooriya - Milpitas CA, US
Hari Krishnan - San Carlos CA, US

G06F 11/263
G06F 11/27
G06F 11/273
G06F 11/14

During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

20230089800, Mar 23, 2023

Sep 17, 2021

17/478736

- Santa Clara CA, US
Venkat Abilash Reddy Nerallapally - San Jose CA, US
Jaison Daniel Kurien - Bangalore, IN
Bonita Bhaskaran - San Jose CA, US
Milind Sonawane - Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US
Purnabha Majumder - Lafayette CA, US

G01R 31/3177

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

20210294791, Sep 23, 2021

Mar 20, 2020

16/826005

- Santa Clara CA, US
Shantanu K. Sarangi - Saratoga CA, US
Hemalkumar Chandrakant Doshi - San Jose CA, US
Hari Unni Krishnan - San Carlos CA, US
Gunaseelan Ponnuvel - San Jose CA, US
Brian Lawrence Smith - Mountain View CA, US

G06F 16/23

Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

20210286693, Sep 16, 2021

Mar 13, 2020

16/818327

- Santa Clara CA, US
Sachin Idgunji - San Jose CA, US
Jue Wu - Los Gatos CA, US
Shantanu Sarangi - Saratoga CA, US

G06F 11/267
G06F 11/22
G06F 11/27
G06F 11/273
G06F 1/3296

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

20200363470, Nov 19, 2020

May 17, 2019

16/416034

- Santa Clara CA, US
Shantanu K. Sarangi - Saratoga CA, US
Sailendra Chadalavada - Saratoga CA, US
Sumit Raj - Bangalore, IN
Rangavajjula Kameswara Naga Mahesh - Narasaraopet, IN
Jayesh Kumar Pandey - San Jose CA, US
Venkat Abilash Reddy Nerallapally - San Jose CA, US

G01R 31/3177

Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.

20190128964, May 2, 2019

Oct 30, 2018

16/175423

- Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US

G01R 31/3185
G06F 13/42
G06T 1/20

A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.

20170115338, Apr 27, 2017

Oct 27, 2016

15/336687

- Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US
Milind Sonawane - San Jose CA, US
Amit Sanghani - San Jose CA, US
Jonathon E. Colburn - Ben Lomond CA, US
Dan Smith - Los Gatos CA, US
Jue Wu - Los Gatos CA, US
Mahmut Yilmaz - Los Altos Hills CA, US

G01R 31/28

In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

20170115345, Apr 27, 2017

Oct 27, 2016

15/336736

- Santa Clara CA, US
Amit Sanghani - San Jose CA, US
Shantanu Sarangi - Saratoga CA, US
Jonathon E. Colburn - Ben Lomond CA, US
Bala Tarun Nelapatla - Santa Clara CA, US
Rajendra Kumar reddy.S - Bangalore, IN
Mahmut Yilmaz - Los Altos Hills CA, US

G01R 31/3177
G01R 31/317

A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.