Shannon A Wichman

6421754, Jul 16, 2002

Jun 7, 1995

08/480179

Weiyuen Kau - Dallas TX
John H. Cornish - Dallas TX
Qadeer A. Qureshi - Round Rock TX
Shannon A. Wichman - Dallas TX

Texas Instruments Incorporated - Dallas TX

G06F 1324

710261, 710262, 710263, 710266, 710129

An electronic system ( ) includes a first integrated circuit (IC) ( ) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ ), and a logic circuit ( ) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate ( ) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate ( ) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit ( ) has a system management interrupt (SMI#) output pin and SMI circuitry ( ) including a SMI register ( ) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC ( ) further has a mask SMI register ( ) connected to the SMI register ( ) to select particular ones of the events sources for SMI response.

6531903, Mar 11, 2003

Aug 14, 2001

09/929183

Shannon A. Wichman - McKinney TX

LSI Logic Corporation - Milpitas CA

H03B 1900

327117, 327115, 327157

The present invention provides a divider circuit for frequency division of input clock signals, and a method operating and a phase-locked loop (PLL) circuit incorporating the same. In one embodiment, the divider circuit includes a counting subcircuit configured to count rising and falling edges of an input signal. In addition, the divider circuit includes, a signal generator configured to provide an output signal by performing an operation on the count of the rising and falling edges of the input signal based on a divisor control signal.

6745314, Jun 1, 2004

Nov 26, 2001

09/994459

Shannon A. Wichman - McKinney TX

LSI Logic Corporation - Milpitas CA

G06F 1200

711214, 711217, 711219, 711169, 712 35, 712209

A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes: (1) address calculation logic, having multiple datapaths, that calculates, from data regarding a buffer operation, an updated address result therefor and (2) modification order determination circuitry, coupled in parallel with the address calculation logic, that transmits a memory access request and the updated address result in an order that is based on whether the buffer operation is pre-modified or post-modified.

6889318, May 3, 2005

Aug 7, 2001

09/924178

Shannon A. Wichman - McKinney TX, US

LSI Logic Corporation - Milpitas CA

G06F009/45

712226

An instruction pipeline for a DSP with fusing logic for combining multiple instructions into a single control word which can be executed by one execution unit. The pipeline fetches a greater number of instructions than the number of execution units to which it can issue instructions. It applies grouping rules to the instructions and also identifies pairs, or larger groups, of instructions which can be combined, or fused, into a single control word which can be executed by one execution unit. Issuance of a fused control word to a single execution unit effectively allows two or more instructions to be executed simultaneously in one execution unit.

6963961, Nov 8, 2005

Jul 9, 2001

09/901455

Charles H. Stewart - Richardson TX, US
Shannon A. Wichman - McKinney TX, US

LSI Logic Corporation - Milpitas CA

G06F013/00

711169, 711154

An improved method of operating a digital signal processor instruction pipeline and a memory interface for implementing the method. Memory store requests are separated into an address phase and a data phase. Store addresses are issued to the interface when ready and held in a queue until the corresponding store data is available. The store data is issued to the interface and held in a queue until its corresponding store address is to be coupled to memory. The pipeline operates more efficiently because it does not have to wait for store data before issuing the address and related control signals. Data coherency is maintained because load and store addresses are issued at the same pipeline stage and executed in the order issued.

6973630, Dec 6, 2005

Apr 7, 2003

10/408387

Tuan Dao - Richardson TX, US
Seshagiri P. Kalluri - Richardson TX, US
Shannon A. Wichman - McKinney TX, US

LSI Logic Corporation - Milpitas CA

G06F017/50

716 1, 716 4

A system for, and method of, reference-modeling a processor design. In one embodiment, the system includes: (1) an architecture database that contains specifications regarding the processor design that include: instruction set specifications, architectural resource specifications, pipeline specifications and connectivity specifications, (2) a simulation subsystem that draws selected portions of the specifications to simulate and test the processor design and (3) a documentation subsystem that draws other selected portions of the specifications to document and register-model the processor design, changes in the specifications being propagated to the architecture database.

7020765, Mar 28, 2006

Sep 27, 2002

10/256410

Hung Nguyen - Plano TX, US
Shannon Wichman - McKinney TX, US

LSI Logic Corporation - Milpitas CA

G06F 9/40

712200, 712215, 712234

A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes multiple registers for storing marking data pertaining to a number of instructions in each of multiple execution pipeline stages. In another embodiment, the processor includes multiple attribute queues simultaneously assignable to a corresponding number of conditional execution instruction groups. In another embodiment, the processor includes write enable logic and an execution unit. The write enable logic produces write enable signals dependent upon received attributes, and the execution unit saves results of instructions of conditional execution instruction groups dependent upon the write enable signals.

7051146, May 23, 2006

Jun 25, 2003

10/603303

Hung T. Nguyen - Plano TX, US
Shannon A. Wichman - McKinney TX, US

LSI Logic Corporation - Milpitas CA

G06F 13/14

710305, 710110, 710260

A processor is disclosed that executes an instruction including a user-defined value (an address or a command) and provides the user-defined value during execution of the instruction. In one embodiment the processor includes a bus interface adapted for coupling to a bus, and the processor drives the user-defined address or command upon one or more signal lines of the bus via the bus interface during execution of the instruction. A described data processing system includes the processor coupled to a device including an addressable register. The device receives a user-defined address from the processor and accesses the addressable register in response to the user-defined address. Methods are disclosed for obtaining a value stored in an addressable register, providing a value stored in an addressable register, storing a value in an addressable register, and modifying a value stored in an addressable register.