Professional Records
License Records
Shahab Ardalan
Address:
2254 Silver Blossom Ct, San Jose, CA 95138
License #:
C1062792
Category:
Airmen
Shahab Ardalan Phones & Addresses
-
14842 Nelson Way, San Jose, CA 95124
Work
Company:
Ayar labs Jan 2018
Position:
High speed serdes design
Education
Degree:
Doctorates, Doctor of Philosophy
School / High School:
University of Waterloo 2003 to 2007
Specialities:
Computer Engineering
Skills
Analog Circuit Design • Mixed Signal • Analog • Circuit Design • Cmos • Verilog • Ic • Asic • Matlab • Semiconductors • Integrated Circuit Design • Signal Processing • Fpga • Vhdl • Cadence Virtuoso • Algorithms • Digital Signal Processors • Vlsi • Integrated Circuits • Serdes • High Speed Link
Industries
Semiconductors
Resumes
Resumes
President
View pageLocation:
San Jose, CA
Industry:
Semiconductors
Work:
Ayar Labs
High Speed Serdes Design
Etopus Technology, Inc. Jun 2016 - Jan 2018
Senior Consultant and Research Scientist
San Jose State University Sep 1, 2012 - Jan 2018
Assistant Professor, Director of Center For Analog and Mixed Signal
Integrion Microelectronics Jan 2012 - Jan 2015
Senior Consultant and High-Speed Link
Gemenid Jan 2012 - Jan 2015
President
High Speed Serdes Design
Etopus Technology, Inc. Jun 2016 - Jan 2018
Senior Consultant and Research Scientist
San Jose State University Sep 1, 2012 - Jan 2018
Assistant Professor, Director of Center For Analog and Mixed Signal
Integrion Microelectronics Jan 2012 - Jan 2015
Senior Consultant and High-Speed Link
Gemenid Jan 2012 - Jan 2015
President
Education:
University of Waterloo 2003 - 2007
Doctorates, Doctor of Philosophy, Computer Engineering
Doctorates, Doctor of Philosophy, Computer Engineering
Skills:
Analog Circuit Design
Mixed Signal
Analog
Circuit Design
Cmos
Verilog
Ic
Asic
Matlab
Semiconductors
Integrated Circuit Design
Signal Processing
Fpga
Vhdl
Cadence Virtuoso
Algorithms
Digital Signal Processors
Vlsi
Integrated Circuits
Serdes
High Speed Link
Mixed Signal
Analog
Circuit Design
Cmos
Verilog
Ic
Asic
Matlab
Semiconductors
Integrated Circuit Design
Signal Processing
Fpga
Vhdl
Cadence Virtuoso
Algorithms
Digital Signal Processors
Vlsi
Integrated Circuits
Serdes
High Speed Link
Publications
Us Patents
Phase Optimization Technique In High-Speed Simultaneous Bidirectional Links
View pageUS Patent:
20190326994, Oct 24, 2019
Filed:
Jul 2, 2019
Appl. No.:
16/460074
Inventors:
- San Jose CA, US
Shahab Ardalan - San Jose CA, US
Shahab Ardalan - San Jose CA, US
International Classification:
H04B 10/43
H04B 10/25
H04B 10/2507
H04B 10/25
H04B 10/2507
Abstract:
A bidirectional transceiver includes a transmitter and a receiver that respectively transmits a local signal to and receives remote signal from a common bidirectional communication channel, thus the bidirectional channel signal is the superimposition of the local and remote signals. The bidirectional transceiver also includes a transmit canceller that substantially removes the local transmitted signal from the superimposed signals on the bidirectional channel before the local receiver. The remote signal is transmitted by a remote transceiver over the bidirectional channel. A sampling phase is set, based on timing information in the received remote signal, and the received signal is sampled. Timing relation of transitions in the local transmit signal relative to the receiver sampling phase is set such that transmit signal cancellation is optimum at receiver sampling phase, by changing the delay applied to the local transmit signal. To keep the timing relation of the local transmit signal relative to the remote transceiver, a second delay is applied to the local transmit signal before transmission into the bidirectional channel that provides a delay substantially same as the first delay but opposite in direction.
Programmable Switching Engine With Storage, Analytic And Processing Capabilities
View pageUS Patent:
20150063349, Mar 5, 2015
Filed:
Aug 27, 2013
Appl. No.:
14/010834
Inventors:
SHAHAB ARDALAN - San Jose CA, US
Mona Mojdeh - Menlo Park CA, US
Mona Mojdeh - Menlo Park CA, US
International Classification:
H04L 12/721
H04L 12/851
H04L 12/933
H04L 12/771
H04L 12/851
H04L 12/933
H04L 12/771
US Classification:
370381
Abstract:
An improvement to the prior-art extends an intelligent solution beyond simple IP packet switching. It intersects with computing, analytics, storage and performs delivery diversity in an efficient intelligent manner. A flexible programmable network is enabled that can store, time shift, deliver, process, analyze, map, optimize and switch flows at hardware speed. Multi-layer functions are enabled in the same node by scaling for diversified data delivery, scheduling, storing, and processing at much lower cost to enable multi-dimensional optimization options and time shift delivery, protocol optimization, traffic profiling, load balancing, and traffic classification and traffic engineering. An integrated high performance flexible switching fabric has integrated computing, memory storage, programmable control, integrated self-organizing flow control and switching.