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Seungjoon J Park

from Los Altos, CA
Age ~59
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Also known as:
Seung Joon Park, Joon Park, Seung J Park, Joo N Park, Seung-Joon Park, N Park
Phone and address:
2148 Deodara Dr, Los Altos, CA 94024
(650) 326-5571
Related to:
Catalina Ji Young Park, 38Yikyung Park, 65Hyun K ParkWonik I Choi, 54Jong Park, 57
Connected to:
Aerin E Park, 57Alex H Park, 52Alfredo B Park, 49Alisa L Park, 83Alisia J Park, 36Alyn S Park, 73Ameca E Park, 48Angela M Park, 45Angela Park, 47Angelia L Park, 58

Seungjoon Park Phones & Addresses

  • 2148 Deodara Dr, Los Altos, CA 94024 (650) 326-5571
  • 1670 El Camino Real, Menlo Park, CA 94025 (650) 326-5571
  • Stanford, CA
  • Santa Clara, CA
  • Mountain View, CA
  • 2148 Deodara Dr, Los Altos, CA 94024

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Publications

Us Patents

Fairness Mechanism For Starvation Prevention In Directory-Based Cache Coherence Protocols

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US Patent:
8099558, Jan 17, 2012
Filed:
Mar 31, 2009
Appl. No.:
12/415929
Inventors:
SeungJoon Park - Los Altos CA, US
Ching-Tsun Chou - Palo Alto CA, US
Akhilesh Kumar - Sunnyvale CA, US
International Classification:
G06F 12/08
US Classification:
711141, 711E12026
Abstract:
Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e. g. , using distributed linked-lists). In turn, the tracked requests may be served in a fair order. Other embodiments are also disclosed.

Optimizing Concurrent Accesses In A Directory-Based Coherency Protocol

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US Patent:
8190820, May 29, 2012
Filed:
Jun 13, 2008
Appl. No.:
12/157792
Inventors:
Hariharan Thantry - Santa Clara CA, US
Akhilesh Kumar - Sunnyvale CA, US
Seungjoon Park - Los Altos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/08
G06F 13/14
US Classification:
711118, 711141, 711144, 711146, 711167, 711E12026
Abstract:
In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed.

Methodology And Tools For Tabled-Based Protocol Specification And Model Generation

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US Patent:
8443337, May 14, 2013
Filed:
Mar 11, 2008
Appl. No.:
12/075390
Inventors:
Ching-Tsun Chou - Palo Alto CA, US
Phanindra K. Mannava - Folsom CA, US
Seungjoon Park - Los Altos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/44
US Classification:
717104, 717142
Abstract:
In one embodiment, the present invention includes a method for associating and storing a code fragment for each cell of a table for a protocol specification in a semantic mapping corresponding to the table, and automatically generating a formal model for the protocol specification using the table and the semantic mapping. Other embodiments are described and claimed.

Cache Coherence Protocol

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US Patent:
20050240734, Oct 27, 2005
Filed:
Apr 27, 2004
Appl. No.:
10/833977
Inventors:
Brannon Batson - Santa Cruz CA, US
Ling Cen - Austin TX, US
William Welch - San Jose CA, US
Herbert Hum - Portland OR, US
Seungjoon Park - Los Altos CA, US
International Classification:
G06F012/00
US Classification:
711141000, 711145000
Abstract:
A cache coherence protocol facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.

Messaging Protocol

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US Patent:
20050262250, Nov 24, 2005
Filed:
Apr 27, 2004
Appl. No.:
10/833965
Inventors:
Brannon Batson - Santa Cruz CA, US
Ling Cen - Austin TX, US
William Welch - San Jose CA, US
Herbert Hum - Portland OR, US
Seungjoon Park - Los Altos CA, US
International Classification:
G06F015/16
US Classification:
709230000
Abstract:
The invention facilitates a messaging protocol in a multi-node system to resolve conflicts at a home node.

System And Method For A 3-Hop Cache Coherency Protocol

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US Patent:
20080162661, Jul 3, 2008
Filed:
Dec 29, 2006
Appl. No.:
11/647618
Inventors:
Phanindra K. Mannava - Folsom CA, US
Robert H. Beers - Beaverton OR, US
SeungJoon Park - Los Altos CA, US
Brannon Baxton - Brooklyn NY, US
International Classification:
G06F 15/16
US Classification:
709213
Abstract:
A system and method for implementing a cache coherency protocol are described. The system includes a first caching agent to send a first cache request to a home agent. The system also includes the home agent including a queue to store the first cache request.

Interconnect Architectural State Coverage Measurement Methodology

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US Patent:
20090171647, Jul 2, 2009
Filed:
Dec 27, 2007
Appl. No.:
11/965158
Inventors:
Phanindra Mannava - Folsom CA, US
Seungjoon Park - Los Altos CA, US
Ajit Dingankar - El Dorado Hills CA, US
Ching-Tsun Chou - Palo Alto CA, US
Nikhil Mittal - Bangalore, IN
Radhakrishnan V. Mahalikudi - Bangalore, IN
Mayank Singhal - Bangalore, IN
International Classification:
G06F 17/30
G06F 9/00
US Classification:
703 21, 707100, 707E17044, 707E17005
Abstract:
A method and apparatus for ensuring efficient validation coverage of an architecture, such as protocol or interconnect architecture, is herein described. A coverage space of states for an architecture is generated and stored in a database. During simulation, states of the coverage space encountered are marked. From this, the states encountered and not encountered may be determined. Based on the states not encountered, a targeted test suite is developed to target at least some of the states not encountered during previous simulation. This feedback loop from simulation to refining of a test suite based on states of a coverage space not encountered during simulation may be recursively repeated until adequate validation, i.e. an adequate confidence level of validation, of the coverage space is achieved.

Adaptive Cache Organization For Chip Multiprocessors

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US Patent:
20090254712, Oct 8, 2009
Filed:
Apr 2, 2008
Appl. No.:
12/061027
Inventors:
Naveen Cherukuri - San Jose CA, US
Ioannis Schoinas - Portland OR, US
Akhilesh Kumar - Sunnyvale CA, US
Seungjoon Park - Los Altos CA, US
Ching-Tsun Chou - Palo Alto CA, US
International Classification:
G06F 12/00
US Classification:
711141, 711E12001
Abstract:
A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core may retrieve a data block from a data storage. An initial amorphous cache bank adjacent to the initial processing core may store an initial data block copy . A home bank directory may register the initial data block copy
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Seungjoon J Park from Los Altos, CA, age ~59 Get Report