Seiichi Te Morimoto

7084053, Aug 1, 2006

Sep 30, 2003

10/676294

Reza M. Golzarian - Beaverton OR, US
Robert P. Meagley - Hillsboro OR, US
Seiichi Morimoto - Beaverton OR, US
Mansour Moinpour - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L 21/44

438610, 438597, 438598, 438615, 438643, 438645, 438652, 438653, 438659, 438678, 438679, 438680, 438626, 438627, 438629

A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.

7405419, Jul 29, 2008

Dec 28, 2005

11/321127

Reza M. Golzarian - Beaverton OR, US
Robert P. Meagley - Hillsboro OR, US
Seiichi Morimoto - Beaverton OR, US
Mansour Moinpour - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L 47/00
H01L 23/52

257 4, 257 41, 257 44, 257132, 257503, 257734, 257735, 257736, 257746, 257750, 257758, 257773, 257774, 257776, 257785

A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.

8334184, Dec 18, 2012

Dec 23, 2009

12/646450

Joseph M. Steigerwald - Forest Grove OR, US
Uday Shah - Portland OR, US
Seiichi Morimoto - Beaverton OR, US
Nancy Zelick - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 21/336
H01L 21/70

438294, 438183, 438197, 257407, 257E21444, 257E21453

Techniques are disclosed for fabricating FinFET transistors (e. g. , double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e. g. , flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e. g. , flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.

50810510, Jan 14, 1992

Sep 12, 1990

7/581292

Wayne A. Mattingly - Rio Rancho NM
Seiichi Morimoto - Beaverton OR
Spencer E. Preston - Portland OR

Intel Corporation - Santa Clara CA

B24B 100
H01L 21302

437 10

An improved method for conditioning the surface of a pad for polishing a dielectric layer formed on a semiconductor substrate is disclosed. In one embodiment, the serrated edge of an elongated blade member is first placed in radial contact with the surface of the polishing pad. The table and the pad are then rotated relative to the blade member. At the same time, the blade member is pressed downwardly against the pad surface such that the serrated edge cuts a plurality of substantially circumferential grooves into the pad surface. These grooves are dimensioned so as to facilitate the polishing process by creating point contacts which increases the pad area and allows more slurry to applied to the substrate per unit area. Depending on the type of pad employed, the number of teeth per inch on the serrated edge, the type of slurry used, etc. , the downward force applied to the blade member in the rotational speed of the table are optimized to obtain the resultant polishing rate and uniformity desired.

47215488, Jan 26, 1988

May 13, 1987

7/049100

Seiichi Morimoto - Aloha OR

Intel Corporation - Santa Clara CA

B44C 122
C03C 1500
C03C 2506

156657

Planarization process for planarizing glass layer which receives first layer metal. Spin-on-glass is cured in steam and then etched back using hydrofluoric and nitric acids diluted in acetic acids.

60812729, Jun 27, 2000

Sep 30, 1997

8/941599

Seiichi Morimoto - Beaverton OR
Timothy L. Deeter - Portland OR

Intel Corporation - Santa Clara CA

G06F 1500

345420

A method for optimally sizing dummy structures in an integrated circuit design is disclosed. Adjacent dummy structures are merged to provide a composite merged dummy structure. Each side of a first dummy structure representation is expanded in a lateral direction by a predetermined distance such that the first dummy structure representation merges with an adjacent second dummy structure representation forming the composite merged dummy structure. The composite merged dummy structure is then examined to determine if it exceeds a predetermined size. If the composite merged dummy structure exceeds the predetermined size, then the composite merged dummy structure is contracted to fit within predetermined perimeters.

59111119, Jun 8, 1999

Sep 2, 1997

8/944041

Mark T. Bohr - Aloha OR
Lawrence N. Brigham - Beaverton OR
Peter K. Moon - Portland OR
Seiichi Morimoto - Beaverton OR

Intel Corporation - Santa Clara CA

H01L 2144

438585

A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

51048280, Apr 14, 1992

Mar 1, 1990

7/487418

Seiichi Morimoto - Beaverton OR
Robert J. Patterson - Beaverton OR

Intel Corporation - Santa Clara CA

H01L 21302
H01L 21463

437225

An improved method for planarizing the surface of an dielectric deposited over a semiconductor substrate. The substrate is pressed face down against a table which has been coated with an abrasive material. In this way, the upper surface of the interlayer dielectric contacts the abrasive. Rotational movement of the wafer relative to the table facilitates removal of the protruding portions of the interlayer dielectric by the abrasive. Post-planarization step height variation is minimized by simultaneously cooling the table and the abrasive material during the abrasive or polishing process. By maintaining the table and the abrasive at about 10 degrees Celsius the step height variation is reduced by a factor of 2 over that normally realized in the prior art.