Sean J Treichler

6724395, Apr 20, 2004

Mar 24, 2000

09/534886

Sean J. Treichler - Cupertino CA

NVIDIA Corporation - Santa Clara CA

G09G 500

345582, 345428

A system, method and article of manufacture are provided for anisotropic filtering during texture sampling. A description of a region, e. g. pixel footprint in a source image, to be texture sampled is initially received. Thereafter, the region is subdivided based on the description into a plurality of samples with a predetermined shape for mapping textures onto the samples. By subdividing the region in the source image into a plurality of samples having a predetermined shape, the region may be covered by samples that may be configured to be more suitable for an underlying process such as MIP mapping, thus allowing efficient texture sampling while reducing blurring, aliasing and other visual artifacts.

6779069, Aug 17, 2004

Sep 4, 2002

10/235143

Sean J. Treichler - Mountain View CA
Edward W. Liu - Milpitas CA

Nvidia Corporation - Santa Clara CA

G06F 1300

710305, 710 62, 710 29, 375219

Apparatus for a baseband-media interface is described. More particularly, in an embodiment, a baseband processor, a medium access controller and a baseband-media interface are provided with a input/output controller as an integrated circuit. In another instance, a baseband processor, a medium access controller and a baseband-media interface are provided on a printed circuit board and coupled to an input/output controller via a bus. The printed circuit board may be a system board or a peripheral card.

6957298, Oct 18, 2005

Sep 8, 2003

10/657957

James M. Van Dyke - Sunnyvale CA, US
Nicholas J. Foskett - Mountain View CA, US
Brad Simeral - San Francisco CA, US
Sean Treichler - Palo Alto CA, US

NVIDIA Corporation - Santa Clara CA

G06F012/00

711105, 711154, 711169

A memory controller system is provided including a plurality of memory controller subsystems each coupled between memory and one of a plurality of computer components. Each memory controller subsystem includes at least one queue for managing pages in the memory. In use, each memory controller subsystem is capable of being loaded from the associated computer component independent of the state of the memory. Since high bandwidth and low latency are conflicting requirements in high performance memory systems, the present invention separates references from various computer components into multiple command streams. Each stream thus can hide activate bank preparation commands within its own stream for maximum bandwidth. A page context switch technique may be employed that allows instantaneous switching from one look ahead stream to another to allow low latency and high bandwidth while preserving maximum bank state from the previous stream.

6980208, Dec 27, 2005

Sep 3, 2002

10/234977

John Montrym - Cupertino CA, US
Jonah M. Alben - San Jose CA, US
Sean Treichler - Mountain View CA, US
John M. Danskin - Cranston RI, US
Gary Tarolli - Concord MA, US

NVIDIA Corporation - Santa Clara CA

G06T015/00

345422

A system, method and computer program product are provided for performing depth testing and blending operations in a first mode and a second mode. In the first mode, a circuit processes a first number (m) of first pixels per clock cycle, each of the first pixels including both color values and depth values. In the second mode, the circuit processes a second number (n) of second pixels per clock cycle. Each of the second pixels includes the depth values and not the color values. Further, the second number (n) is greater than the first number (m).

7042263, May 9, 2006

Dec 18, 2003

10/742572

Philip Browning Johnson - Los Gatos CA, US
Jonah M. Alben - San Jose CA, US
Sean Jeffrey Treichler - Mountain View CA, US
Adam E. Levinthal - Redwood City CA, US

NVIDIA Corporation - Santa Clara CA

H03K 3/356

327199, 327200, 327407, 327159, 326 38, 326 40

Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.

7117238, Oct 3, 2006

Sep 19, 2002

10/247115

Nicholas J. Foskett - Adelaide, AU
Sean Treichler - Mountain View CA, US

NVIDIA Corporation - Santa Clara CA

G06F 7/38
G06F 7/52

708502, 708605, 708654

A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set of Taylor's series coefficients for each segment of the input value range. Other aspects of the invention are methods for determining preferred parameters for elements of such a circuit, a circuit designed in accordance with such a method, and a system (e. g. , a pipelined graphics processor) for and method of pipelined graphics data processing using any embodiment of the circuit. The preferred parameters are determined by minimizing the circuit's size subject to constraints on input and output value format and output accuracy, assuming a specific function to be approximated and a specific degree for the approximation but allowing variation of parameters such as coefficient width and number of input value range segments.

7187220, Mar 6, 2007

Dec 18, 2003

10/741149

Jonah M. Alben - San Jose CA, US
Sean Jeffrey Treichler - Mountain View CA, US
Adam E. Levinthal - Redwood City CA, US

Nvidia Corporation - Santa Clara CA

H03L 7/06

327156, 327159, 327160

Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

7240179, Jul 3, 2007

Dec 13, 2004

11/012025

Sean Jeffrey Treichler - Mountain View CA, US
Brad W. Simeral - San Franciso CA, US
David G. Reed - Saratoga CA, US
Roman Surgutchik - Santa Clara CA, US

NVIDIA Corporation - Santa Clara CA

G06F 9/26
G06F 9/34
G06F 12/00

711203, 711202, 711220, 711165

A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.