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Sean Kainuma Phones & Addresses

  • Westminster, CO
  • Denver, CO
  • Honolulu, HI
  • Johnson City, NY
  • Rochester, NY

Publications

Us Patents

Voltage Level Shifting

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US Patent:
7504860, Mar 17, 2009
Filed:
Jul 31, 2008
Appl. No.:
12/184010
Inventors:
Sean Toshio Kainuma - Johnson City NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19/0175
US Classification:
326 68, 326 81
Abstract:
A system comprising, a sense portion comprising a NAND logic gate that receives a first input logic signal associated with a lower voltage, wherein the sense portion outputs a sense logic signal, an intermediary portion comprising, a node operative to output an intermediary signal, a first pull down device, wherein the first pull down device receives a second input logic signal associated with the lower voltage complimentary with respect to the first input logic signal, a first pull up device that receives the sense logic signal, wherein the first pull up device is connected to a power supply at the higher operating voltage, and a second pull up device that receives the output logic signal associated with a higher voltage, an inverter portion, outputting the first output logic signal associated with the higher voltage responsive to a state of the intermediary signal.

Efficient Method For Locating A Short Circuit

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US Patent:
7503023, Mar 10, 2009
Filed:
Apr 30, 2008
Appl. No.:
12/112529
Inventors:
Sean T. Kainuma - Johnson City NY, US
Michael K. Kerr - Johnson City NY, US
Raymond H. Kim - Endicott NY, US
Joseph H. Underwood - Apalachin NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 5
Abstract:
A method of locating a short circuit of a shorted circuit path in a circuit layout includes receiving a connecting stack of the circuit layout, receiving the circuit layout defining the connecting stack, receiving at least four virtual probe locations, identifying shortest paths between the at least four virtual probes, and outputting an intersection of the shortest paths, the intersection including the location of the short circuit. According to the method, the connecting stack includes interconnecting paths representing conductive traces of a circuit design, the at least four virtual probe locations exist on the interconnecting stack on at least two different nodes along the shorted circuit path, and the shortest paths are identified between pairs of the at least four probes and are between the at least two different nodes.
Sean T Kainuma from Westminster, CO, age ~42 Get Report