Resumes
Resumes
Se Yang Phones & Addresses
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San Jose, CA
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Cupertino, CA
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Chestnut Hill, MA
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Cambridge, MA
Publications
Us Patents
Package-On-Package Assembly With Wire Bond Vias
View pageUS Patent:
20130093087, Apr 18, 2013
Filed:
Feb 24, 2012
Appl. No.:
13/404408
Inventors:
Ellis Chau - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 23/498
US Classification:
257738, 257737, 257784, 257E23069, 257E23068
Abstract:
A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25 and 90 relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
Package-On-Package Assembly With Wire Bond Vias
View pageUS Patent:
20130093088, Apr 18, 2013
Filed:
Feb 24, 2012
Appl. No.:
13/405108
Inventors:
Ellis Chau - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Zhijun Zhao - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Zhijun Zhao - San Jose CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 23/498
H01L 21/56
H01L 21/56
US Classification:
257738, 257784, 438124, 257E23069, 257E2306, 257E21502
Abstract:
A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.
Package-On-Package Assembly With Wire Bond Vias
View pageUS Patent:
20130095610, Apr 18, 2013
Filed:
Feb 24, 2012
Appl. No.:
13/404458
Inventors:
Ellis Chau - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 21/60
H01L 21/58
H01L 21/56
H01L 21/58
H01L 21/56
US Classification:
438109, 438123, 257E21506, 257E21502, 257E21505
Abstract:
A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25 and 92 relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
Hydrophobicity Modulating Underwater Chemical Sensor
View pageUS Patent:
20130171738, Jul 4, 2013
Filed:
Jun 17, 2011
Appl. No.:
13/704934
Inventors:
Hyungryul Johnny Choi - Cambridge MA, US
Ayse Asatekin Alexiou - Somerville MA, US
Se Young Yang - Cambridge MA, US
Christy D. Petruczok - Cambridge MA, US
Karen K. Gleason - Cambridge MA, US
Nicholas M. Patrikalakis - Cambridge MA, US
George Barbastathis - Boston MA, US
Ayse Asatekin Alexiou - Somerville MA, US
Se Young Yang - Cambridge MA, US
Christy D. Petruczok - Cambridge MA, US
Karen K. Gleason - Cambridge MA, US
Nicholas M. Patrikalakis - Cambridge MA, US
George Barbastathis - Boston MA, US
Assignee:
MASSACHUSETTS INSTITUTE OF TECHNOLOGY - Cambridge MA
International Classification:
G01N 27/06
US Classification:
436150, 422 8202
Abstract:
A chemical sensor that works while being submerged in a highly conductive medium is described. The chemical sensor includes hydrophobic structures that are distributed on conductive electrodes and are separated by small air cavities while submerged in the conductive medium. The hydrophobic structures are arranged such that their hydrophobicity varies in response to exposure to a target analyte. The change in the level of hydrophobicity results in permeation of the conductive liquid on to the conductive electrodes, thereby reducing the resistance levels between the conductive electrodes. The sensor indicates presence of the target analyte in response to detection of a change in resistance between at least two of the conductive electrodes.
Package-On-Package Assembly With Wire Bond Vias
View pageUS Patent:
20130200533, Aug 8, 2013
Filed:
Mar 12, 2013
Appl. No.:
13/795811
Inventors:
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 23/00
US Classification:
257784, 438127
Abstract:
A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
Tsv Fabrication Using A Removable Handling Structure
View pageUS Patent:
20130313012, Nov 28, 2013
Filed:
May 22, 2012
Appl. No.:
13/477586
Inventors:
Se Young Yang - Cupertino CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Michael Huynh - Santa Clara CA, US
Rajesh Katkar - San Jose CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Michael Huynh - Santa Clara CA, US
Rajesh Katkar - San Jose CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H05K 3/22
H05K 1/11
H05K 1/11
US Classification:
174266, 174261, 216 13, 216 20
Abstract:
A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.
Package-On-Package Assembly With Wire Bond Vias
View pageUS Patent:
20130328219, Dec 12, 2013
Filed:
Aug 14, 2013
Appl. No.:
13/966636
Inventors:
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 23/00
US Classification:
257784
Abstract:
A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.
Thin Wafer Handling And Known Good Die Test Method
View pageUS Patent:
20140054763, Feb 27, 2014
Filed:
Aug 23, 2012
Appl. No.:
13/593118
Inventors:
Charles G. Woychik - San Jose CA, US
Se Young Yang - Cupertino CA, US
Pezhman Monadgemi - Fremont CA, US
Terrence Caskey - Santa Cruz CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Se Young Yang - Cupertino CA, US
Pezhman Monadgemi - Fremont CA, US
Terrence Caskey - Santa Cruz CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/00
H01L 23/498
H01L 23/498
US Classification:
257737, 438107, 438 15, 438125
Abstract:
A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.