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Se Y Yang

from Fremont, CA
Age ~56
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Also known as:
Se E Yang, Se Y Vang, Cse Yang
Related to:
Rocky V Yang, 41Tong VangDao L Vang, 48Daneng LyLisa Vang Bla, 43Tinoi Y Yang, 47Andrew Vang, 32Cse YangSee Vang, 29Jennifer T Dang, 64Lee M Vang, 54Roger H VangMee Yang, 66Teng Vang, 53Kim M Vang, 52Frank E Vang, 34Shoua Vang, 62K Vang Pa, 68Lilly Vang, 55
Connected to:
Abby Yang, 32Addison Yang, 44Aileen C Yang, 51Alexandria L Yang, 33Allerina Yang, 33Alyssa J Yang, 36Amee Yang, 32Amy Yang, 57Andrew Yang, 34Anna Yang, 40

Se Yang Phones & Addresses

  • Fremont, CA
  • Hanford, CA
  • 9990 Pianella Way, Elk Grove, CA 95757 (916) 685-7918
  • Sacramento, CA
  • Turlock, CA
  • Stockton, CA

Publications

Us Patents

Package-On-Package Assembly With Wire Bond Vias

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US Patent:
20130093087, Apr 18, 2013
Filed:
Feb 24, 2012
Appl. No.:
13/404408
Inventors:
Ellis Chau - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 23/498
US Classification:
257738, 257737, 257784, 257E23069, 257E23068
Abstract:
A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25 and 90 relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.

Package-On-Package Assembly With Wire Bond Vias

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US Patent:
20130093088, Apr 18, 2013
Filed:
Feb 24, 2012
Appl. No.:
13/405108
Inventors:
Ellis Chau - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Zhijun Zhao - San Jose CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 23/498
H01L 21/56
US Classification:
257738, 257784, 438124, 257E23069, 257E2306, 257E21502
Abstract:
A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

Package-On-Package Assembly With Wire Bond Vias

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US Patent:
20130095610, Apr 18, 2013
Filed:
Feb 24, 2012
Appl. No.:
13/404458
Inventors:
Ellis Chau - San Jose CA, US
Reynaldo Co - Santa Cruz CA, US
Roseann Alatorre - San Martin CA, US
Philip Damberg - Cupertino CA, US
Wei-Shun Wang - Palo Alto CA, US
Se Young Yang - Cupertino CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 21/60
H01L 21/58
H01L 21/56
US Classification:
438109, 438123, 257E21506, 257E21502, 257E21505
Abstract:
A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25 and 92 relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.

Tsv Fabrication Using A Removable Handling Structure

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US Patent:
20130313012, Nov 28, 2013
Filed:
May 22, 2012
Appl. No.:
13/477586
Inventors:
Se Young Yang - Cupertino CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Michael Huynh - Santa Clara CA, US
Rajesh Katkar - San Jose CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H05K 3/22
H05K 1/11
US Classification:
174266, 174261, 216 13, 216 20
Abstract:
A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.

Thin Wafer Handling And Known Good Die Test Method

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US Patent:
20140054763, Feb 27, 2014
Filed:
Aug 23, 2012
Appl. No.:
13/593118
Inventors:
Charles G. Woychik - San Jose CA, US
Se Young Yang - Cupertino CA, US
Pezhman Monadgemi - Fremont CA, US
Terrence Caskey - Santa Cruz CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/00
H01L 23/498
US Classification:
257737, 438107, 438 15, 438125
Abstract:
A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

3D Thin Profile Pre-Stacking Architecture Using Reconstitution Method

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US Patent:
20180204820, Jul 19, 2018
Filed:
Jan 17, 2017
Appl. No.:
15/408263
Inventors:
- Cupertino CA, US
Chonghua Zhong - Cupertino CA, US
Kunzhong Hu - Cupertino CA, US
Se Young Yang - San Jose CA, US
International Classification:
H01L 25/065
H01L 23/00
H01L 23/498
H01L 23/31
H01L 25/18
H01L 21/48
H01L 21/56
H01L 25/00
H01L 21/768
H01L 21/683
H01L 21/78
Abstract:
Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.

Double Side Mounting Memory Integration In Thin Low Warpage Fanout Package

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US Patent:
20160300813, Oct 13, 2016
Filed:
Apr 7, 2015
Appl. No.:
14/680539
Inventors:
- Cupertino CA, US
Kunzhong Hu - Cupertino CA, US
Chonghua Zhong - Cupertino CA, US
Mengzhi Pang - Cupertino CA, US
Se Young Yang - San Jose CA, US
International Classification:
H01L 25/065
H01L 25/00
Abstract:
Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.

System In Package Fan Out Stacking Architecture And Process Flow

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US Patent:
20160260684, Sep 8, 2016
Filed:
Mar 4, 2015
Appl. No.:
14/638925
Inventors:
- Cupertino CA, US
Kunzhong Hu - Cupertino CA, US
Kwan-Yu Lai - Campbell CA, US
Mengzhi Pang - Cupertino CA, US
Chonghua Zhong - Cupertino CA, US
Se Young Yang - San Jose CA, US
International Classification:
H01L 25/065
H01L 25/00
Abstract:
Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.
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Se Y Yang from Fremont, CA, age ~56 Get Report