Scott T Haban

6779125, Aug 17, 2004

Jun 9, 2000

09/590596

Scott Haban - Austin TX

Cirrus Logic, Inc. - Austin TX

G06F 104

713500, 327157

Clock generation circuitry includes an oscillator for generating a first signal from a crystal of a selected oscillating frequency. A first frequency multiplier selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency. A second frequency multiplier selectively multiplies the frequency of the third signal by a third factor to obtain a fourth signal of a selected frequency, the second and third factors selected to produce a fourth signal having a frequency of a preselected multiple of a second set of.

7233970, Jun 19, 2007

Feb 16, 2002

10/078252

Greg North - Austin TX, US
Scott Haban - Austin TX, US
Kyle Stein - Austin TX, US

Cipher Corporation Limited - Stoneham MA

G06F 7/38
H04K 1/00

708491, 380 28

A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, Xand X. Xand Xare exponentiated to compute, respectively, Cand C. Cand Care merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

7613913, Nov 3, 2009

Mar 21, 2006

11/385520

Scott Haban - Austin TX, US
G. Tyson Tuttle - Austin TX, US
Gregory A. Hodgson - Pflugerville TX, US

Silicon Laboratories Inc. - Austin TX

G06F 9/24

713 1, 713 2, 713100

In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.

7882282, Feb 1, 2011

May 21, 2008

12/154265

Scott Haban - Austin TX, US
Dylan Hester - Austin TX, US
Ruifeng Sun - Austin TX, US

Silicon Laboratories Inc. - Austin TX

G06F 13/00
H04N 5/44

710 38, 710 52, 710110, 348725

A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

8024392, Sep 20, 2011

May 9, 2007

11/801333

Greg North - Austin TX, US
Scott Haban - Austin TX, US
Kyle Stein - Austin TX, US

nCipher Corporation Limited - Stoneham MA

G06F 7/38

708491

A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, Xand X. Xand Xare exponentiated to compute, respectively, Cand C. Cand Care merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

8151029, Apr 3, 2012

Dec 30, 2010

12/981769

Scott Haban - Austin TX, US
Dylan Hester - Austin TX, US
Ruifeng Sun - Austin TX, US

Silicon Laboratories Inc. - Austin TX

G06F 13/00

710316, 710 38, 710 52, 710110

A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

8264387, Sep 11, 2012

Mar 31, 2006

11/396097

Lawrence Der - Austin TX, US
George Tyson Tuttle - Austin TX, US
Alessandro Piovaccari - Austin TX, US
Chunyu Xin - Austin TX, US
Scott Haban - Austin TX, US
Javier Elenes - Austin TX, US
Dan Kasha - Seattle WA, US
Peter Vancorenland - Austin TX, US

Silicon Laboratories Inc. - Austin TX

H03M 1/00

341110, 341144, 341155

A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

8331887, Dec 11, 2012

Dec 30, 2009

12/650166

George Tyson Tuttle - Austin TX, US
Younes Djadi - Austin TX, US
Russell Croman - Austin TX, US
Scott Thomas Haban - Austin TX, US
Javier Elenes - Austin TX, US
Lokesh Duraiappah - Austin TX, US

Silicon Laboratories Inc. - Austin TX

H04B 7/08
H04K 3/00

455132

In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.