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Saurabh A Mookerjea

from Belle Mead, NJ
Age ~43
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Also known as:
Saurabh M Mookerjea
Connected to:
Shubo Mookerjee, 47Satrajit Mookherjee, 55Justin T Mool, 45Saritha D Moola, 45Srikanth Moola, 33Sudhir Moola, 43Grace M Moolchan, 77Priyanka Moolchandani, 30Johan Moolenaar, 85Charrise Moolenoar, 54

Saurabh Mookerjea Phones & Addresses

  • Belle Mead, NJ
  • Princeton, NJ
  • Franklin Park, NJ
  • Hillsboro, OR
  • State College, PA
  • Las Vegas, NV
  • Pelham, AL
  • Gainesville, FL

Work

Company: Intel Oct 2010 Position: Device engineer

Education

Degree: PhD School / High School: Penn State University 2007 to 2010 Specialities: Electrical Engineering

Skills

Cmos • Semiconductors • Jmp • Semiconductor Device • Simulations • Semiconductor Industry • Nanotechnology • Soc • Characterization • Ic • Matlab • Thin Films • 1. Cmos Device Architecture Design/Model... • 2. Semiconductor Device Characterization... • 3. Statistical Data Analysis • 4. Back End and Front End Test Chip Deve... • 5. Strong Device Fabrication Experience • 7. Strong Inter Personal and Communicati... • Design of Experiments • Process Integration • Yield • Process Simulation • Integrated Circuits • System on A Chip • Materials Science • Physics • Electronics • Research and Development • Statistical Process Control • Engineering • Photolithography • Manufacturing

Languages

English • Hindi • Marathi • Bengali

Industries

Semiconductors

Resumes

Resumes

Saurabh Mookerjea Photo 1

Senior Test And Analytics Engineer

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Location:
47 York Dr, Princeton, NJ 08540
Industry:
Semiconductors
Work:
Intel since Oct 2010
Device Engineer
Education:
Penn State University 2007 - 2010
PhD, Electrical Engineering University of Mumbai 1999 - 2003
BE, Electrical Engineering University of Florida
Skills:
Cmos
Semiconductors
Jmp
Semiconductor Device
Simulations
Semiconductor Industry
Nanotechnology
Soc
Characterization
Ic
Matlab
Thin Films
1. Cmos Device Architecture Design/Modeling and Analysis
2. Semiconductor Device Characterization on Automated and Hand Probers
3. Statistical Data Analysis
4. Back End and Front End Test Chip Development With Scaled Pitches
5. Strong Device Fabrication Experience
7. Strong Inter Personal and Communication Skills
Design of Experiments
Process Integration
Yield
Process Simulation
Integrated Circuits
System on A Chip
Materials Science
Physics
Electronics
Research and Development
Statistical Process Control
Engineering
Photolithography
Manufacturing
Languages:
English
Hindi
Marathi
Bengali

Publications

Us Patents

Tfet Based 6T Sram Cell

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US Patent:
20120106236, May 3, 2012
Filed:
Oct 27, 2010
Appl. No.:
12/912904
Inventors:
Jawar Singh - University Park PA, US
Ramakrishnan Krishnan - Hsinchu, TW
Saurabh Mookerjea - Hillsboro OR, US
Suman Datta - Port Matilda PA, US
Vijaykrishnan Narayanan - State College PA, US
Assignee:
THE PENN STATE RESEARCH FOUNDATION - UNIVERSITY PARK PA
International Classification:
G11C 11/419
US Classification:
365154
Abstract:
Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.
Control profile
Saurabh A Mookerjea from Belle Mead, NJ, age ~43 Get Report