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Sanjay K Sancheti

from Santa Clara, CA
Age ~53
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Also known as:
Sanjay Kumar Sancheti, Sanjay Te Sancheti, Sanjay J Sancheti, Saniay Sancheti, Sancheti Sk, Jay San
Phone and address:
4682 Snead Dr, Santa Clara, CA 95054
(408) 980-9622
Related to:
Sahil SanchetiPraveena Sancheti, 77Parveen Sancheti, 49
Connected to:
Ashok K Sancheti, 68Gaurav Sancheti, 52Sonal K Sancheti, 53A Sanchez, 72Acevedo L Sanchez, 39Ada M Sanchez, 78Adairis Sanchez, 40Adalia D Sanchez, 80Adda T Sanchez, 67Adelaida C Sanchez, 47

Sanjay Sancheti Phones & Addresses

  • 4682 Snead Dr, Santa Clara, CA 95054 (408) 980-9622
  • Sunnyvale, CA
  • 500 Louisville St, Starkville, MS 39759 (662) 338-9400
  • San Jose, CA
  • 500 Louisville St APT 6, Starkville, MS 39759 (662) 338-9400

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Sanjay Sancheti Photo 1

Strategic Product Development Director

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation
Strategic Product Development Director
Cypress Semiconductor Corporation
Senior Strategic Product Development Manager
Cypress Semiconductor Corporation 2006 - 2011
Design Engineering Manager and Program Manager
Cypress Semiconductor Corporation 2004 - 2006
Principal Design Engineer
Education:
Mississippi State University 2000 - 2002
Master of Science, Masters Indian Institute of Technology, Kanpur 1990 - 1994
Bachelors, Electronics Engineering Cotton College 1987 - 1989
Skills:
Soc
Semiconductors
Mixed Signal
Ic
Analog
Asic
Simulations
Analog Circuit Design
Verilog
Eda
Usb
Cmos
Static Timing Analysis
Embedded Systems
System on A Chip
Power Management
Rtl Design
Engineering Management
Vlsi
Integrated Circuit Design
Semiconductor Industry
Dft
Circuit Design
Vhdl
Silicon
Program Management
Application Specific Integrated Circuits
Integrated Circuits
Sram
Languages:
Hindi
Sanjay Sancheti Photo 2

Sanjay Sancheti

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Publications

Us Patents

Method And System For High Resolution Delay Lock Loop

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US Patent:
6710636, Mar 23, 2004
Filed:
Oct 3, 2002
Appl. No.:
10/264692
Inventors:
Gary Gibbs - San Jose CA
Lingsong Xu - Newark CA
Sanjay Sancheti - Starkville MS
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03L 706
US Classification:
327158, 327161
Abstract:
A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop.

Delay Circuit That Scales With Clock Cycle Time

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US Patent:
7019576, Mar 28, 2006
Filed:
Mar 18, 2004
Appl. No.:
10/804988
Inventors:
Sanjay K. Sancheti - Starkville MS, US
Suwei Chen - Mississippi State MS, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03H 11/26
US Classification:
327261, 327285
Abstract:
A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.

Multi-Port Memory Cell And Access Method

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US Patent:
7113445, Sep 26, 2006
Filed:
Sep 22, 2004
Appl. No.:
10/948006
Inventors:
Sanjay Sancheti - Sunnyvale CA, US
Jeffery Scott Hunt - Ackerman MS, US
George M. Ansel - Starkville MS, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 8/00
US Classification:
36523005, 365154
Abstract:
A multi-port memory cell () can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell () can be cleared by shorting complementary data nodes (- and -) together. Write data can then be placed on a bit line. Complementary data nodes (- and -) can then be isolated once again, resulting in the write data being latched within the memory cell (). An access method () for a multi-port memory cell is also described.

Data Path Configurable For Multiple Clocking Arrangements

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US Patent:
7132854, Nov 7, 2006
Filed:
Sep 23, 2004
Appl. No.:
10/949537
Inventors:
Suwei Chen - Redmond WA, US
Sanjay Sancheti - Sunnyvale CA, US
Jeffery Scott Hunt - Ackerman MS, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 19/173
H03K 3/289
US Classification:
326 46, 326 93, 327202, 327407
Abstract:
A data path () can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path () can be compact circuit structure, needing only an additional mode multiplexer () and inverter over a conventional D-type master-slave flip-flop.

System And Method For Reducing Skew In Complementary Signals That Can Be Used To Synchronously Clock A Double Data Rate Output

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US Patent:
7135899, Nov 14, 2006
Filed:
May 13, 2004
Appl. No.:
10/844719
Inventors:
Sanjay Sancheti - Starkville MS, US
Suwei Chen - Starkville MS, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03L 7/00
US Classification:
327144, 341101
Abstract:
A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit. Also, the circuit, system, and method support double data rate (DDR) data and echo clock generation, where the echo clock transitions in sync with the DDR output.

Wide Frequency Range Dll With Dynamically Determined Vcdl/Vco Operational States

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US Patent:
7233183, Jun 19, 2007
Filed:
Feb 6, 2004
Appl. No.:
10/774180
Inventors:
Sanjay K. Sancheti - Starkville MS, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03L 7/06
US Classification:
327158, 327149, 327156, 331 11
Abstract:
In one embodiment of the present invention, a phase generator, comprising a plurality of delay blocks, is coupled in a feedback loop with a phase detector. When in an open loop mode, the phase generator is operable as a voltage controlled delay line. The phase detector compares an input signal with a first output signal of the phase generator and generates a first control signal based thereon. The phase generator is also coupled in a feedback loop with a phase-frequency detector. When in a closed loop mode, the phase generator is operable as a voltage controlled oscillator and the phase-frequency detector compares the input signal with a second output signal of the phase generator. The phase-frequency detector then generates a second control signal based thereon.

Arbiter Circuit And Signal Arbitration Method

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US Patent:
7383370, Jun 3, 2008
Filed:
Mar 20, 2006
Appl. No.:
11/384748
Inventors:
Sanjay Sancheti - Sunnyvale CA, US
Gareth Feighery - San Mateo CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 13/00
US Classification:
710241, 326 94, 327 19
Abstract:
An arbiter circuit () can include a latch circuit () that latches competing input signals (MATCH and MATCH) to generate signals on latch output (- and -). A filter section () can prevent metastable states of latch output signals from propagating through to output signals (BUSY and BUSY). In addition, filter section () can generate output signals (BUSY and BUSY) having one set of values when both inputs are inactive, and a second set of values when latch () is in the metastable state.

Configurable Power Controller

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US Patent:
7863971, Jan 4, 2011
Filed:
Nov 27, 2007
Appl. No.:
11/998009
Inventors:
Anup Nayak - Fremont CA, US
Sanjay Kumar Sancheti - Sunnyvale CA, US
Shailja Garg - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03K 17/74
G11C 5/14
US Classification:
327546, 327543, 365227, 365229
Abstract:
A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.
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Sanjay K Sancheti from Santa Clara, CA, age ~53 Get Report